Integrated Clock Gating Cell With On-Demand Inverted Clock
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Solution Overview
Problem
Conventional integrated clock gating cells consume significant clock switching power due to the use of a clock and an inverted clock signal, which toggles every time the clock switches, leading to increased power consumption.
Innovation Solution
A low power integrated clock gating cell that includes an input condition determination circuit to generate a temporary inverted clock signal only when needed, coupled with an enable control logic circuit and a latch circuit, which uses the temporary inverted clock signal and inverted output signal to control the latch, reducing unnecessary toggling and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional ICG uses a clock signal to control the latch, then the clock gating function is achieved, but significant clock switching power is consumed
Solution Approach 1:
The patent applies dynamics by making the clock signal path dynamically controllable through the enable signal. The latch is dynamically enabled or disabled based on the enable input, allowing the clock to reach the latch only when needed. This dynamic control eliminates unnecessary clock switching when the latch is disabled, directly reducing clock switching power while maintaining reliable clock gating functionality.
Solution Approach 2:
The patent implements periodic action by allowing the clock signal to periodically reach the latch only when the enable signal is active. When enabled, the latch responds to clock edges; when disabled, the clock signal is blocked. This periodic transmission of the clock signal based on enable conditions reduces the frequency of unnecessary clock switching events, thereby reducing power consumption while preserving the essential clock gating function.
2Loss of energy
If an ICG uses both clock and inverted clock signals to pass enable data to latch, then data transmission is achieved, but the ICG toggles every time the clock switches increasing power consumption
Solution Approach 1:
The patent extracts and eliminates the unnecessary inverted clock signal generation from the conventional ICG design. By removing the requirement for both clock and inverted clock signals, the patent prevents the latch from toggling on every clock edge. Instead, only the necessary clock signal is used in conjunction with the enable signal, extracting the harmful element (continuous toggling) while preserving the essential data transmission function through the enabled latch.
Solution Approach 2:
The patent inverts the conventional approach by using the enable signal to control clock transmission to the latch, rather than using the clock signal to control data transmission. This inversion of control logic prevents the latch from unnecessarily toggling on every clock edge. The enable signal determines whether the latch is transparent or opaque to the clock, fundamentally inverting the control mechanism to reduce power consumption while maintaining data transmission capability.
Data Source
AI summary
Embodiments include an integrated clock gating (ICG) cell. The low power ICG cell may include an input condition determination circuit configured to generate a temporary inverted clock signal and an inverted output signal. The low power ICG cell may include an enable control logic circuit configured to receive the temporary inverted clock signal and the inverted output signal from the input condition determination circuit. The low power ICG cell may include a latch circuit coupled to the enable control logic circuit and configured to latch an input value dependent on at least the inverted output signal and the temporary inverted clock signal. The input condition determination circuit is configured to generate the temporary inverted clock signal only when it is needed.