Clock Gating Mechanism for At-Speed Scan Testing Power Droop
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Solution Overview
Problem
During at-speed testing of integrated circuits, a rapid shift from quiescent to active phases causes a power droop in the power grid, leading to potential device failure or reduced operational speed, which may result in false negatives, and existing solutions like testing at lower speeds or switching fewer transistors increase test times.
Innovation Solution
A computer-implemented method for designing a clock gating mechanism that includes generating a model to limit current draw, modifying the netlist, and applying test vectors to determine if the clock gating mechanism meets performance metrics, utilizing a plurality of clock gating circuits and logic circuits to control the system clock and power distribution within the integrated circuit device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the device is tested at rated speed during capture phase, then test accuracy is improved, but power droop occurs causing false negatives
Solution Approach 1:
The device is divided into multiple clock domains, each independently controllable. During capture phase, only the clock domain containing the DUT is activated while other domains are gated off, segmenting the power consumption and preventing global power droop that would cause false negatives.
Solution Approach 2:
The clock gating mechanism dynamically adjusts clock distribution based on test phase. Clock gates are conditionally enabled or disabled based on whether the device is in scan-load or capture phase, allowing the system to adapt power distribution to current operational requirements.
2Reliability
If the device is tested at lower speed to avoid power droop, then false negatives are reduced, but test time increases
Solution Approach 1:
By segmenting the clock distribution into independently controllable domains, the system can maintain rated speed for the DUT while gating other domains. This allows high-speed accurate testing without the power droop that would otherwise force slower testing speeds.
3Reliability
If fewer transistors are switched during capture phase to reduce current demand, then power droop is reduced, but test coverage requires more test vectors
Solution Approach 1:
The clock gating mechanism segments power consumption by domain rather than limiting the number of switched transistors. This allows full test coverage with appropriate number of vectors while maintaining power grid stability through localized clock control.
Solution Approach 2:
Power management is applied locally to specific clock domains rather than globally. Each domain can be independently enabled or disabled, allowing the DUT to receive full power for complete test coverage while other domains are gated to maintain overall power grid stability.
Data Source
AI summary
A clock gating mechanism controls power within an integrated circuit device. One or more clock gating circuits are configured to couple a system clock to a different portion of the integrated circuit device. A logic circuit applies an enabling signal to one of the clock gating circuits to control whether the system clock passes through the clock gating circuit to a portion of the integrated circuit device associated with the clock gating circuit. A plurality of scan flip-flops is configured to provide a binary code to the logic circuit, where the binary code indicates to the logic circuit that the enabling signal should be applied to the clock gating circuit. One advantage of the disclosed technique is that power droop during at-speed testing of a device is reduced without significantly increasing the quantity of test vectors or reducing test coverage, resulting in greater test yields and lower test times.