Multi-Domain Clock Gating Power Modeling via Three Simulations
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Solution Overview
Problem
Traditional clock gating techniques for multi-domain circuits result in inefficient power usage due to underloaded local clock buffers, and existing power modeling methods lack accuracy and efficiency, especially in complex circuits with numerous small domains.
Innovation Solution
A method involving three targeted simulations is employed to estimate power consumption in micro gated clocking local clock buffer circuits, including determining global and local clock capacitances to accurately calculate power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional clock gating techniques with standard Local Clock Buffers are used for each domain, then clock gating functionality is provided, but power usage becomes inefficient due to underloaded buffers in circuits with numerous small domains
Solution Approach 1:
The patent merges multiple underloaded local clock buffers into a single shared clock buffer that serves multiple domains. This is achieved by implementing a multi-domain clock gating circuit where one clock buffer instance is shared across several domains, each controlled by separate enable signals. This consolidation eliminates the redundancy of multiple underloaded buffers while maintaining the ability to gate clocks at the domain level, thereby improving power usage efficiency.
2Loss of energy
If multi-domain clock gating circuits with shared LCBs are implemented, then power savings are achieved, but power modeling and analysis become more complex
Solution Approach 1:
The patent segments the power consumption into distinct components: global clock buffer power, global enable power, and individual domain enable powers. By breaking down the total power consumption into these separable parts, each associated with specific capacitances and control signals, the complexity of power modeling is managed through systematic decomposition rather than treating the entire circuit as a single complex unit.
Solution Approach 2:
The patent introduces specific capacitance parameters (global clock capacitance, global enable capacitance, local clock capacitance) to model the electrical characteristics of the shared clock buffer and its control signals. By expressing power consumption in terms of these measurable electrical parameters, the model becomes more tractable and analyzable, transforming the complex behavioral modeling into a more manageable parameter-based approach.
3Loss of energy
If a single LCB drives multiple domains with separate enable signals, then power consumption is reduced, but accuracy in power estimation becomes difficult to achieve
Solution Approach 1:
The patent performs preliminary simulations to extract capacitance values for the global clock buffer, global enable signal, and local clock domains before final power estimation. By conducting these simulations in advance under controlled conditions, the necessary electrical characteristics are obtained and stored, allowing for accurate power calculation without requiring complex real-time measurement and analysis during actual circuit operation.
Data Source
AI summary
Embodiments of the disclosure include a method for estimating the power consumption of a micro gated clocking local clock buffer circuit. The method involves obtaining a model of the circuit with a global enable input and multiple local clock enable inputs. It includes performing three simulations: a first simulation with the global enable off to determine global clock capacitance, a second simulation with the global enable on and local enables off to determine global enable capacitance, and a third simulation with the global enable on and local enables active to determine local clock capacitances. The power consumption is then calculated based on the global clock capacitance, the global enable capacitance, and the local clock capacitance for each of the local clock enable inputs.