Clock Gating Power Savings Computation for IC Design
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Solution Overview
Problem
Current IC design techniques for clock gating are inefficient in computing power savings for candidate registers, particularly as they do not account for different clock gating techniques and are limited to existing clock gates, leading to suboptimal power and area costs.
Innovation Solution
A method is introduced to compute power savings in clock gating circuits by identifying candidate registers through tracing forward and backward in combinational and sequential logic, using virtual buffers and logic insertion to estimate power consumption, and generating a script for implementation tools to apply the best clock-gating technique based on power and area savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional clock gating techniques are used with predefined thresholds or manual selection, then the design process is simpler, but power savings are suboptimal and area costs increase
Solution Approach 1:
The system performs self-analysis by automatically computing power savings for each candidate register through trace-forward and trace-backward operations, eliminating the need for manual selection or predefined thresholds. The implementation tool autonomously identifies optimal clock gating opportunities and generates appropriate scripts.
Solution Approach 2:
The method performs preliminary power savings computation during the design phase by analyzing candidate registers before final implementation. This advance calculation of power savings enables informed decision-making about which registers to clock gate, optimizing both power reduction and area utilization before the design is finalized.
2Use of energy by moving object
If all registers are clock gated to maximize power savings, then power consumption decreases, but the size of the IC increases
Solution Approach 1:
Instead of uniformly applying clock gating to all registers, the system computes power savings individually for each candidate register and selectively applies clock gating only to those with significant power savings potential. This localized approach ensures that clock gating resources are allocated to the most beneficial locations, maximizing power reduction while minimizing area overhead.
Solution Approach 2:
The method applies clock gating partially rather than universally by computing power savings for each candidate register and selecting only those that meet optimization criteria. This partial application of clock gating achieves substantial power savings without the excessive area cost of gating all registers.
3Ease of manufacture
If existing clock gating methods are used, then implementation is straightforward, but power savings computation is limited to existing clock gates only
Solution Approach 1:
The system provides a universal framework that handles multiple clock gating techniques (traditional clock gates, enable signals, and other gating methods) through a unified power savings computation approach. The trace-forward and trace-backward operations work across different gating paradigms, making the tool versatile while maintaining ease of implementation through automated script generation.
Data Source
AI summary
A method for computing the power savings in an integrated circuit (IC) design is disclosed. The method computes the difference in power savings between techniques used for clock gating. Based on the computation results, the method outputs a script to control the implementation tool so as to provide for the best implementation clock gating technique in terms of power and area savings.