Clock Gating Circuit Topology for Lower Dynamic Clock Power
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces issues with clock signal synchronization and power consumption in clock trees, leading to performance errors and area inefficiencies as ICs become smaller and more complex.
Innovation Solution
A clock gating circuit is implemented, comprising a NOR logic gate, a transmission gate, and a cross-coupled pair of transistors, which reduces the number of transistors toggled by the inverted clock signal, resulting in lower dynamic clock power consumption and reduced area occupancy compared to other clock gating cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If a conventional clock gating circuit is used to distribute clock signals, then clock signal distribution is achieved, but dynamic clock power consumption increases and area occupancy increases
Solution Approach 1:
The patent combines the clock gating functionality with a compact circuit structure that integrates the NOR logic gate, transmission gate, and cross-coupled transistors into a unified design. This merging of functions reduces the overall transistor count while maintaining clock gating capability, thereby reducing both power consumption and area occupancy simultaneously.
Solution Approach 2:
The patent changes the circuit topology parameters by using a specific configuration of cross-coupled transistors and a transmission gate controlled by the NOR logic gate output. This parameter change in circuit architecture reduces the number of toggling transistors, which directly reduces dynamic power consumption without proportionally increasing area.
2Reliability
If more transistors are used in the clock gating circuit, then clock signal control capability is improved, but dynamic clock power consumption increases
Solution Approach 1:
The patent extracts only the essential transistors needed for clock gating functionality by using a cross-coupled pair configuration with a transmission gate. This extraction removes unnecessary transistors from the conventional design, maintaining reliable clock signal control while reducing the number of toggling transistors and thus dynamic power consumption.
3Adaptability or versatility
If the clock tree is made more complex to handle synchronization, then clock signal distribution coverage is improved, but power consumption increases and area increases
Solution Approach 1:
The patent creates a universal clock gating cell design that can be deployed throughout the clock tree to handle synchronization requirements. The multi-functional circuit structure performs both clock gating and synchronization functions, providing wide distribution coverage without proportionally increasing power consumption or area.
Data Source
AI summary
A clock gating circuit includes an input circuit, a cross-coupled pair of transistors, a first transistor, a first pull-up transistor and an output circuit. The input circuit is coupled to a first and second node, and is configured to receive a first and second enable signal, and to set a first control signal of the first node responsive to the first or second enable signal. The cross-coupled pair of transistors is coupled between the first and second node. The first pull-up transistor includes a first gate terminal configured to receive a clock input signal, a first drain terminal coupled to the second node, and a first source terminal coupled to a voltage supply. The output circuit is coupled between the second node and an output node, and configured to output an output clock signal responsive to the second control signal.