Automatic Clock-Gating Propagation in Microprocessor Circuits

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Solution Overview

Problem

Automated tools fail to effectively identify and implement clock-gating opportunities in microprocessor systems, leading to inefficiencies in power consumption and heat management due to manual limitations and oversight of clock-gating opportunities during mapping and logic optimization.

Innovation Solution

A method and system for automatically inserting clock-gating logic by identifying sender and enable-generating memory elements, generating enable signals, and propagating clock-gating from downstream seed memory elements to upstream sender memory elements, using data inputs and combinational logic to replicate and time-shift enable signals, thereby reducing switching power.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual clock-gating identification is used, then clock-gating opportunities can be identified, but the process is tedious and time-consuming, limiting it to only a small subset of sequential elements

Engineering Contradiction:

Improveclock-gating identification accuracyVSAvoidclock-gating implementation time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system performs self-service by automatically identifying clock-gating opportunities and inserting clock-gating logic without requiring manual intervention. The automated tool traverses the circuit, identifies seed memory elements with clock-gating opportunities, and propagates enable signals to sender memory elements, making the entire process self-executing and eliminating the time-consuming manual approach

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The patent introduces an intermediary automated analysis tool that acts as a mediator between the circuit design and clock-gating implementation. This tool traverses the circuit, identifies clock-gating opportunities by analyzing data paths and enable signals, and systematically inserts clock-gating logic, thereby bridging the gap between manual identification accuracy and automated efficiency

Inventive Principle:

Principle #24Intermediary (Mediator)

2Extent of automation

If automated tools operate on high-level RTL model, then automation is achieved, but clock-gating opportunities in the final gate-level netlist are missed

Engineering Contradiction:

Improveclock-gating insertion automationVSAvoidclock-gating opportunity detection accuracy

Core Design Contradiction:

Extent of automationVSMeasurement precision

Solution Approach 1:

The system performs preliminary action by conducting clock-gating analysis at the gate-level netlist stage rather than at the high-level RTL model stage. This ensures that all optimization transformations, buffering, and logic changes are already reflected in the circuit representation, allowing the automated tool to accurately detect clock-gating opportunities in the final implementation

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent inverts the conventional approach by performing clock-gating insertion after mapping and logic optimization rather than before. This reverse sequencing ensures that the automated tool operates on the actual final circuit structure, capturing all clock-gating opportunities that may have been created or modified by prior optimization steps

Inventive Principle:

Principle #13The other way round (Inversion)

3Loss of energy

If clock-gating is implemented, then switching power is reduced, but additional logic circuitry must be added to selectively disable clock signals

Engineering Contradiction:

Improveswitching power consumptionVSAvoidcircuit logic complexity

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The system merges the enable signal generation logic into existing combinational logic paths that already determine when memory elements need to update. By reusing existing enable signals from seed memory elements and propagating them to sender memory elements, the implementation avoids adding redundant logic while achieving comprehensive clock-gating coverage

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent creates universal enable signal paths that serve multiple memory elements simultaneously. A single enable signal generated from combinational logic can gate clocks for multiple sender memory elements that share the same data dependency, thereby reducing overall circuit complexity while maintaining effective power management across the circuit

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8533648B2Automatic clock-gating propagation technique

Publication Date: 2013.09.10 ORACLE INT CORP

AI summary

Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.