Clock Gating Pulse Level Shifter for Fast Low-Power Flip-Flops
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Solution Overview
Problem
Existing digital systems face challenges in achieving high-speed and low-power operation due to limitations in latch design, particularly in combinational and sequential circuits, where the amplitude and duration of clock signals and enable signals impact power consumption and performance.
Innovation Solution
A clock gated circuit is introduced, comprising a pulse generator and a pulse level shifter, where the pulse generator receives a clock signal to generate pulses and an inverted pulse, and the pulse level shifter converts the pulse level using an enable signal, operating with different power supply voltages to produce a pulse clock signal with a higher amplitude and shorter active interval, thereby reducing power consumption and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal amplitude is increased to improve flip-flop performance, then the switching speed improves, but the power consumption increases
Solution Approach 1:
The patent applies different voltage levels to different parts of the circuit: the pulse generator operates at a first voltage level while the pulse level shifter converts to a second, higher voltage level. This allows the clock signal to have high amplitude where needed (in the pulse level shifter and flip-flop) while other parts of the circuit operate at lower voltages, thus improving switching speed locally without proportionally increasing overall power consumption.
Solution Approach 2:
The patent uses periodic pulse generation synchronized with the clock signal. The pulse generator creates narrow pulses at specific clock edges, and the pulse level shifter converts these pulses to higher voltage levels. This periodic action ensures that high-voltage signals are applied only during necessary switching intervals rather than continuously, reducing overall power consumption while maintaining flip-flop performance.
2Reliability
If the enable signal duration is extended to ensure proper latching, then the reliability improves, but the duration of short currents increases
Solution Approach 1:
The pulse generator produces pulses that are synchronized with the clock signal edges, preparing the circuit state in advance for the upcoming latch operation. By generating the pulse at the appropriate clock edge and using the pulse level shifter to convert it to a higher voltage level, the circuit ensures that the latching action occurs at the optimal moment, maintaining reliability while minimizing the duration of current flow.
Data Source
AI summary
A clock gated circuit includes a pulse generator and a pulse level shifter. The pulse generator is driven by a first power supply voltage and is configured to receive a clock signal to generate a pulse and an inverted pulse. The pulse level shifter is driven by a second power supply voltage higher than the first power supply voltage and is configured to receive the pulse and the inverted pulse and to convert a level of the pulse in response to an enable signal.