Clock Gating Cell Feedback Latch to Prevent Race Conditions
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Solution Overview
Problem
Integrated circuits face challenges in reducing power consumption and area while preventing malfunction due to race conditions in clock gating operations, which existing clock gating cells fail to address effectively.
Innovation Solution
The proposed clock gating cell design includes a set-reset (SR) latch structure with a feedback transistor that avoids race conditions by preventing pull-up or pull-down of a critical node, using a combination of logic gates and transistors to manage clock signals efficiently, thereby reducing power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional clock gating cell is used to reduce power consumption, then power consumption is reduced, but race conditions may occur causing circuit malfunction
Solution Approach 1:
The patent introduces a feedback transistor as an intermediary element that mediates between the clock signal and the internal node. This feedback transistor prevents race conditions by controlling the timing of signal transitions, ensuring that the clock gating operation completes reliably before power consumption benefits take effect. The intermediary transistor acts as a buffer that eliminates the harmful race condition while preserving the power reduction benefit.
Solution Approach 2:
The patent implements a feedback mechanism where the output of the logic gate is fed back to control the feedback transistor. This feedback loop ensures that the clock gating operation only completes when the internal node reaches the correct logic level, preventing race conditions. The feedback mechanism monitors the internal state and adjusts the clock signal transmission accordingly, ensuring reliable operation while maintaining low power consumption.
2Area of stationary object
If the clock gating cell structure is simplified to reduce area, then area is reduced, but race condition prevention capability is weakened
Solution Approach 1:
The patent merges the feedback transistor with the existing logic gate structure, combining multiple functions into a single integrated unit. The feedback transistor is seamlessly integrated into the logic gate, allowing the cell to maintain reduced area while gaining race condition prevention capability. This merging approach eliminates the need for separate feedback circuits, achieving both area reduction and reliability improvement simultaneously.
Solution Approach 2:
The feedback transistor serves multiple functions: it prevents race conditions, controls clock signal transmission, and maintains logic level stability. By making this single transistor multi-functional, the patent avoids adding extra components that would increase area. The universal feedback transistor handles multiple reliability-critical tasks within the compact cell structure, achieving both small area and strong race condition prevention.
Data Source
AI summary
An integrated circuit may include a clock gating cell based. The clock gating cell may include a first 2-input logic gate configured to receive a clock input and a first signal and generate a second signal, an inverter configured to receive the second signal and generate a clock output, and a 3-input logic gate including a second 2-input logic gate configured to generate the first signal. The first 2-input logic gate and the second 2-input logic gate form a set reset (SR) latch by being cross-coupled, the 3-input logic gate includes a feedback transistor configured to exclusively receive an internal signal of the first 2-input logic gate, and an activation of the feedback transistor by the internal signal is configured to avoid a race condition by preventing a pull-up or a pull-down of a first node at which the first signal is generated.