Clock Gating Sequence for Low-Peak Current Resetting
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Solution Overview
Problem
Existing clock supply technologies face challenges in reducing peak current consumption during resetting operations of semiconductor integrated circuit devices, leading to higher power consumption and manufacturing costs due to incomplete resetting and overlapping clock cycles among circuit blocks.
Innovation Solution
A clock supply apparatus that supplies clock signals with different rising timings to each circuit block during resetting, preventing overlapping of clock cycles and ensuring complete resetting while reducing peak current consumption by using a control signal generation unit and clock gating cells to manage clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock signals are supplied to all circuit blocks simultaneously during resetting operation, then resetting speed is improved, but peak current consumption increases
Solution Approach 1:
The patent divides the simultaneous resetting operation into sequential segments by supplying clock signals to different circuit blocks at different timings. The resetting operation is segmented into multiple phases where each circuit block is reset in turn rather than all at once, thereby reducing the peak current consumption while still achieving complete resetting of all blocks.
Solution Approach 2:
The patent employs periodic action by using clock gating cells that enable clock signals to be supplied periodically to different circuit blocks during resetting. The clock signals are activated in a periodic sequence across different blocks, allowing the resetting operation to spread out current consumption over time rather than concentrating it at a single moment.
2Power
If clock gating is applied to reduce power consumption during resetting, then current consumption is reduced, but resetting completeness deteriorates
Solution Approach 1:
The patent implements feedback mechanisms through control signal generation units that monitor the resetting state of each circuit block. Based on this feedback, the system dynamically adjusts the clock signal supply timing to ensure that all blocks are completely reset before normal operation resumes, thereby maintaining resetting completeness while optimizing power consumption.
Solution Approach 2:
The patent applies preliminary action by preparing and sequencing the clock signal supply to each circuit block before the actual resetting operation begins. The control signal generation units pre-coordinate the timing of clock signals to all blocks, ensuring that resetting is initiated in an optimized sequence that guarantees completeness while minimizing peak current consumption.
3Power
If independent clocks are supplied to circuit blocks to prevent overlapping resetting periods, then instantaneous current consumption is reduced, but device complexity increases
Solution Approach 1:
The patent employs universality by using a single clock source that is distributed to multiple circuit blocks through clock gating cells. Rather than providing independent clock sources for each block, the system uses one universal clock signal that is selectively enabled or disabled for different blocks via control signals, thereby reducing device complexity while still achieving non-overlapping resetting periods.
Solution Approach 2:
The patent introduces intermediary elements in the form of clock gating cells and control signal generation units that mediate between the single clock source and the various circuit blocks. These intermediaries manage the timing and distribution of clock signals, preventing overlapping resetting periods without requiring complex independent clock sources for each block.
Data Source
AI summary
A clock supply apparatus for supplying clock signals to a plurality of circuit blocks includes a supply unit configured to supply, to reset the plurality of circuit blocks, a clock signal rising at timing different from one circuit block to another to each of the plurality of circuit blocks.