Clock Gating Cell Bypass Logic for Reliable Scan Testing
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Solution Overview
Problem
Conventional clock gating cells in scan chains face challenges in meeting enabling conditions during scan testing, leading to incomplete or failed tests, and there is a need for a more suitable design that can efficiently manage clock signals and test signals.
Innovation Solution
A clock gating cell comprising a selector, two latches, an OR gate, and two AND gates, which selectively outputs clock enable or scan input signals based on test enable and bypass signals, allowing for flexible operation in both functional and scan testing modes, and includes a mechanism to force the output of the clock signal in scan testing modes to ensure continuous scanning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock gating cell is used in a scan chain, then the circuit structure is simple, but the scan testing cannot be performed properly because the enabling conditions of the clock gating cell are not met
Solution Approach 1:
The clock gating cell is segmented into multiple functional modules: a selector module that chooses between clock enable signal and scan input signal, a first latch module for signal storage, an OR gate module for logic operations, and a first AND gate module for clock signal generation. This segmentation allows each module to perform its specific function independently, ensuring proper scan testing operation while maintaining clear functional separation.
Solution Approach 2:
The clock gating cell is designed with multi-functionality to operate in both functional mode and scan testing mode. The selector module enables the circuit to switch between receiving clock enable signals (functional mode) and scan input signals (scan testing mode), making the same circuit structure universally applicable to both operating modes without requiring separate dedicated circuits.
2Ease of operation
If the clock gating cell meets enabling conditions during scan testing, then the scan test can be performed, but the circuit complexity increases
Solution Approach 1:
The selector module acts as an intermediary between the control logic and the latch module. It receives both the clock enable signal and the scan input signal, along with a mode selection signal, and automatically selects the appropriate signal to pass to the latch. This intermediary function simplifies the overall operation by centralizing the signal selection logic in one module, making scan testing easier to implement despite the increased structural complexity.
Data Source
AI summary
A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.