Clock Gating for Scan Flip-Flops With Timing Exception Isolation
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Solution Overview
Problem
Existing scan chain test technologies face increased test pattern requirements, test time, and cost due to unknown data values generated by timing exception paths during transition delay fault tests.
Innovation Solution
A clock control circuit and method that includes a first gate control circuit, a first gate circuit, a second gate control circuit, and a second gate circuit, configured to control the flow of clock signals and data outputs to prevent unknown data values from reaching the at-speed domain during transition delay fault tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan chain test is performed under transition delay fault, then test coverage is improved, but unknown data values are generated due to timing exception paths
Solution Approach 1:
The patent introduces a clock control circuit as an intermediary component between the scan flip-flop circuit and the at-speed domain. This circuit includes gate control circuits and gate circuits that selectively control clock signal transmission based on test mode signals, thereby preventing unknown data values from propagating to the at-speed domain while maintaining test coverage
2Reliability
If test pattern amount is increased to cover timing exception paths, then test completeness is improved, but test time increases
Solution Approach 1:
The patent extracts and isolates the timing exception domain from the at-speed domain using a clock control circuit. By selectively blocking clock signals to specific domains based on test mode, the circuit prevents unknown data values from timing exception paths from affecting the at-speed domain, thereby reducing the test pattern amount required while maintaining test completeness
3Stability of the object's composition
If clock signal is continuously provided to scan flip-flop circuit, then circuit operation is maintained, but unknown data values propagate to at-speed domain
Solution Approach 1:
The patent implements dynamic control of clock signal transmission through gate control circuits that respond to test mode signals. The clock control circuit dynamically adjusts clock signal distribution - providing clock signals during normal operation while blocking them during specific test phases - thereby preventing unknown data values from propagating while maintaining circuit operational stability
Data Source
AI summary
The present disclosure provides a clock control circuit and method for a circuitry. The circuitry includes a scan flip-flop circuit, an at-speed domain and a timing exception domain. The scan flip-flop circuit is configured to output data to the at-speed domain and the timing exception domain. The clock control circuit includes a first gate control circuit, a first gate circuit, a second gate control circuit and a second gate circuit. The first gate circuit is controlled by a first control signal output by the first gate control circuit, a scan enable signal and a scan mode signal to block or output a clock signal to the scan flip-flop circuit. The second gate circuit is controlled by a second control signal output by the second gate control circuit to block or output an output signal of the scan flip-flop circuit to the timing exception domain.