Clock Gating Circuit Using Split Threshold Voltages for Low Delay
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining low delay characteristics while reducing power dissipation, particularly due to the trade-off between leakage current and switching speed, which is affected by transistor threshold voltage settings in clock gating cells.
Innovation Solution
The semiconductor device employs a clock circuit with a control circuit having a higher threshold voltage than the output circuit, using low threshold voltage transistors in the AND circuit to maintain low delay characteristics and reduce power dissipation by suppressing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low threshold voltage transistors are used in clock gating cells, then switching speed is improved and delay characteristics are reduced, but leakage current increases and power dissipation worsens
Solution Approach 1:
The patent applies different threshold voltage characteristics to different parts of the clock gating cell circuit. Specifically, transistors in the latch circuit portion are designed with high threshold voltage to minimize leakage current, while transistors in the AND circuit portion are designed with low threshold voltage to maintain fast switching speed and low delay characteristics. This local differentiation resolves the contradiction by optimizing each sub-circuit for its specific function.
Solution Approach 2:
The clock gating cell is segmented into functionally distinct portions: a latch circuit portion and an AND circuit portion. Each portion is independently optimized with appropriate transistor threshold voltages. The latch circuit uses high threshold voltage transistors for low leakage, while the AND circuit uses low threshold voltage transistors for fast switching. This segmentation allows simultaneous optimization of both power consumption and speed performance.
2Loss of energy
If high threshold voltage transistors are used in clock gating cells, then leakage current is reduced and power dissipation is lowered, but switching speed decreases and delay characteristics worsen
Solution Approach 1:
Different threshold voltage characteristics are assigned to different functional blocks within the clock gating cell. The latch circuit portion employs high threshold voltage transistors to achieve low leakage current and reduced power dissipation, while the AND circuit portion employs low threshold voltage transistors to maintain fast switching speed. This localized optimization resolves the contradiction by matching transistor characteristics to functional requirements.
Solution Approach 2:
The clock gating cell is divided into two segmented portions with different transistor threshold voltage characteristics. The latch circuit segment uses high threshold voltage transistors optimized for low power consumption, while the AND circuit segment uses low threshold voltage transistors optimized for high speed operation. This segmentation enables the circuit to achieve both low power dissipation and fast switching speed simultaneously.
Data Source
AI summary
According to a certain embodiment, the semiconductor device includes a circuit block and a clock circuit configured to supply a clock signal to the circuit block at a specific timing. The clock circuit includes an output circuit configured to provide the clock signal to the circuit block, and a control circuit configured to control the timing at which the output circuit provides the clock signal. A threshold voltage of at least a transistor in the output circuit using the clock signal as input/output signals is a first threshold voltage, and a threshold voltage of a transistor configuring the control circuit is a second threshold voltage higher than the first threshold voltage.