Clock Gating Cell Using SR Latch to Cut Dynamic Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock gating technologies consume significant power due to the toggling of numerous transistors in clock gating cells, leading to increased dynamic power consumption and larger footprint, which is inefficient for portable devices.
Innovation Solution
A clock gating system utilizing a set-reset latch instead of a traditional pass-gate latch, incorporating a pair of cross-coupled NOT-AND (NAND) gates, reduces the number of transistors and dynamic power consumption by minimizing the number of transistors that toggle with each clock signal transition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional clock gating cells with pass-gate latch are used, then the clock gating function is achieved, but the number of transistors toggling with each clock signal is large, leading to high dynamic power consumption
Solution Approach 1:
The patent merges the keeper circuit latch with the clock gating logic by sharing transistors between the two functions. Specifically, the pass-transistor latch uses the same transistors (T1, T2, T3, T4) that are part of the clock gating cell logic, eliminating the need for separate latch transistors and reducing the total number of toggling transistors from 9 to 5 per clock cycle.
Solution Approach 2:
The patent makes the clock gating cell transistors serve dual purposes: they perform both the clock gating function (enabling/disabling clock output) and the latch function (holding the enable state). This multi-functionality reduces the overall transistor count and minimizes the number of transistors that need to toggle during clock cycles.
2Area of stationary object
If conventional clock gating cells with pass-gate latch are used, then the clock gating function is achieved, but the circuit footprint is large
Solution Approach 1:
The patent combines the keeper circuit and clock gating logic into a single integrated cell structure. By merging the latch function with the clock gating logic, the physical footprint is reduced as both functions share the same transistor components and circuit area, rather than requiring separate dedicated regions for each function.
Solution Approach 2:
The multi-functional transistors that serve both clock gating and latch purposes reduce the overall component count, directly shrinking the circuit footprint. The shared transistor implementation means fewer physical devices are required on the chip, leading to compact area utilization.
3Productivity
If conventional clock gating cells are used, then clock gating functionality is provided, but numerous transistors toggle with each clock signal transition
Solution Approach 1:
The patent merges the clock gating control logic with the latch circuitry, causing fewer transistors to toggle during clock transitions. The shared transistor implementation means that when the clock is gated, fewer transistors switch states compared to conventional designs, directly reducing dynamic power consumption proportional to the reduced switching activity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.