Clock Gating Circuit With Delayed Enable for DRAM Standby Power
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Solution Overview
Problem
Conventional clock enable signals in memory devices like DRAM result in persistent power consumption during standby modes due to the continuous activation of the synchronous clock enable signal, even when the clock enable signal is at a high level.
Innovation Solution
A clock signal gating circuit comprising a clock signal input buffer, first and second logic circuits, and a latch circuit, which utilizes phase comparison and delayed synchronous clock enable signals to deactivate the clock input buffer during standby, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the synchronous clock enable signal remains active when the clock enable signal is at a high level, then the clock signal input buffer continues to operate, but power consumption increases during standby mode
Solution Approach 1:
The patent implements dynamic control of the clock enable signal by introducing a gating mechanism that adjusts the clock signal buffer's operation state based on system activity. The gated clock enable signal dynamically transitions between active and inactive states, allowing the clock buffer to operate only when necessary while entering a low-power state during standby, thus resolving the contradiction between maintaining clock continuity and reducing power consumption
Solution Approach 2:
The patent changes the operational parameters of the clock signal buffer by controlling its enable signal. By modifying the enable signal's state (active/inactive) based on system conditions, the buffer's power consumption is adjusted without compromising its ability to maintain clock signal integrity when needed, effectively addressing the power consumption issue during standby mode
2Use of energy by moving object
If the clock signal input buffer is deactivated during standby mode, then power consumption is reduced, but clock signal continuity may be affected
Solution Approach 1:
The patent implements preliminary action by ensuring the clock signal buffer is fully activated before it is needed and properly deactivated after standby mode begins. The gating mechanism proactively manages the buffer's operation state, preventing partial or delayed activation/deactivation that could compromise clock signal continuity, thus allowing safe deactivation during standby while maintaining reliability
Data Source
AI summary
A clock signal gating circuit including a clock signal input buffer, a first logic circuit, a second logic circuit, and a latch circuit is provided. The clock signal input buffer receives a clock signal and outputs an internal clock signal based on a clock switch signal. The first logic circuit receives an asynchronous clock enable signal and a synchronous clock enable signal and outputs the clock switch signal. The second logic circuit receives the asynchronous clock enable signal, the synchronous clock enable signal, and the internal clock signal and outputs a clock gating signal. The latch circuit receives the asynchronous clock enable signal and the clock gating signal to output the synchronous clock enable signal.