Clock Gating Circuit Using Ternary Logic to Cut Transistor Area
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Solution Overview
Problem
Conventional clock gating circuits in modern circuit designs face an area penalty due to the use of tri-state inverters, which require 4 transistors each, leading to inefficiencies in circuitry space.
Innovation Solution
The implementation of clock gating circuitry using a ternary logic function with less than four transistors, specifically CMOS transistors, to provide a ternary logic response, reducing the area occupied and improving power efficiency by selectively inactivating flip-flops during inactive states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If tri-state inverters are used to provide three-state logic functions, then the output port can assume a high impedance state to effectively remove the output from the circuitry, but the area occupied by the circuitry increases due to requiring 4 transistors for each tri-state inverter
Solution Approach 1:
The patent changes the fundamental logic parameter from conventional binary logic to ternary logic, enabling three-state logic functions (logic 0, logic 1, and high impedance state) to be achieved with fewer transistors. Specifically, the ternary logic circuit uses 3 transistors instead of the 4 transistors required by traditional tri-state inverters, reducing the circuitry area while maintaining the high impedance capability.
2Loss of energy
If conventional clock gating circuits are used with tri-state inverters, then power saving is achieved by inactivating flip-flops, but the area penalty increases due to the 4-transistor tri-state inverter implementation
Solution Approach 1:
The patent applies ternary logic to the clock gating circuit, changing the operational parameter from binary to three-state logic. This allows the clock signal to be gated into three states (active, inactive, and high impedance) using fewer transistors. The ternary logic clock gating circuit achieves the same power-saving effect by selectively inactivating flip-flops while reducing the area occupied by the gating mechanism itself.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.