Clock Gating for IC Testing Power Reduction
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Solution Overview
Problem
Integrated circuit device testing consumes substantial power due to clock state changes in untested device portions, even when outputs are held in a constant state.
Innovation Solution
Gating off clock signals to components that consume power when clocked, even when not active, by using clock gating circuitry to prevent clock signals from reaching these components during testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are applied to all components during testing, then testing coverage is improved, but power consumption increases due to clock state changes in untested portions
Solution Approach 1:
The patent segments the clock distribution network into multiple independent clock trees, each serving specific components or regions of the integrated circuit. During testing, only the clock tree(s) corresponding to the components under test remain active, while other clock trees are gated off. This segmentation allows selective clocking of component groups, reducing power consumption in untested regions while maintaining adequate clocking for tested regions.
Solution Approach 2:
The patent implements dynamic clock gating control where clock signals are selectively enabled or disabled based on the testing requirements. Clock gating circuitry dynamically adjusts which clock trees are active during different test phases, allowing the system to adapt power distribution to the current testing needs rather than maintaining a static all-or-nothing clocking approach.
2Use of energy by moving object
If clock signals are gated off to reduce power consumption, then power usage is improved, but testing capability may be degraded if not properly managed
Solution Approach 1:
By dividing the clock distribution into multiple independent clock trees that can be selectively activated, the system maintains the capability to test different component combinations. Each clock tree can be independently controlled, allowing flexible configuration of which components are clocked and tested at any given time, thus preserving testing versatility while reducing power consumption.
Solution Approach 2:
The patent introduces clock gating circuitry as an intermediary between the clock source and the various clock trees. This intermediary layer provides fine-grained control over clock signal distribution, enabling selective enabling/disabling of clock trees based on testing requirements. The clock gating circuitry acts as a mediator that balances power reduction goals with testing capability requirements.
Data Source
AI summary
A method of testing an integrated circuit device that includes components of first and second types, where the components of the second type consume power when clocked even when not active, includes gating off the clock signal to prevent clock signals from reaching the components of the second type, and applying test inputs to the components of the first type. Gating off the clock signals to the components of the second type may include preventing the clock signals from reaching individual components of the second type, or preventing the clock signals from reaching each clock tree branch that contains only components of the second type, or, when a clock tree serving the components of the second type supplies clock signals only to the components of the second type, preventing the clock signals from reaching the clock tree.