Clock Gating Verification Using Toggle Cover Sign-Off
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Clock gating verification in circuit designs is computationally intensive and difficult to prove equivalence due to the addition of clock gating logic, which increases circuit area and power consumption, making it challenging to verify the modified design's equivalence to the original.
Innovation Solution
A method and system for clock gating verification using sequential equivalence checking (SEQ) that quantifies verification quality through toggle cover properties, identifying toggle cover properties for nets in the fan-in of integrated clock gating cells, and performing sign-off based on these properties to ensure equivalence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock gating logic is added to reduce power dissipation, then power consumption is reduced, but circuit area increases
Solution Approach 1:
The patent extracts the verification problem from the entire circuit design by focusing specifically on toggle cover properties of nets driving sequential components. This isolation allows for targeted verification of clock gating functionality without requiring exhaustive verification of the entire modified circuit, thereby reducing the verification overhead that would otherwise necessitate larger circuit buffers.
2Use of energy by moving object
If clock gating logic is added to reduce power dissipation, then power consumption is reduced, but verification complexity increases
Solution Approach 1:
The patent changes the verification approach from functional equivalence checking to toggle cover property analysis. By transforming the verification problem into checking whether nets toggle in both the original and modified designs, the complexity is reduced to a manageable parameter-based analysis rather than full functional verification.
Solution Approach 2:
The patent replaces the mechanical/functional verification system with a property-based analysis system. Instead of simulating or functionally verifying the clock gating behavior, the system uses toggle cover properties as a substitute metric that correlates with functional equivalence but requires simpler verification.
3Reliability
If exhaustive verification is performed to ensure equivalence, then verification accuracy is improved, but computational intensity increases
Solution Approach 1:
The patent applies partial verification by checking only toggle cover properties rather than performing exhaustive functional verification. This partial action provides sufficient assurance of equivalence for clock gating operations without the computational burden of complete verification, achieving an optimal balance between accuracy and computational intensity.
Data Source
AI summary
A method or system for clock gating verification of a circuit design. The system identifies a set of sequential components of the circuit design, and a set of nets of the circuit design. Each net is configured to provide a signal to a clock pin of a sequential component. The system then identifies a subset of nets that are associated with toggle signals, each of which transitions between two different signal values. For each of the subset of nets, the system determines one or more toggle cover properties. The system also determines a depth of at least one net in the subset of nets, and performs sign off for the clock gating verification based on the toggle cover properties and the depth of the at least one net.