Clock Gating Circuit Placement Upstream of Buffers
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Solution Overview
Problem
In semiconductor integrated circuit design, existing clock gating circuits are often placed downstream of clock buffers, which hampers their effectiveness in reducing power consumption due to their placement and timing.
Innovation Solution
A design device that automatically configures a semiconductor integrated circuit by setting and inserting clock gating circuits upstream of clock buffers, separating logical elements based on delay times to optimize clock gating, thereby reducing power consumption across the logic circuit and clock buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a clock gating circuit is inserted downstream of a clock buffer, then the power consumption in the logic circuit is reduced, but the performance of the logic circuit deteriorates due to improper timing control
Solution Approach 1:
Instead of placing the clock gating circuit downstream of the clock buffer as in conventional designs, this patent inverts the placement by positioning the clock gating circuit upstream of the clock buffer. This inversion allows the enable signal to control the clock buffer directly, ensuring proper timing control while maintaining power consumption reduction benefits.
Solution Approach 2:
The clock gating circuit is placed upstream of the clock buffer to perform preliminary action on the clock signal before it reaches the buffer. By controlling the clock buffer's operation in advance through the enable signal, the system achieves both power savings and proper timing control without affecting logic circuit performance.
2Device complexity
If a single clock gating circuit is used for multiple logical elements, then the device complexity is reduced, but the power consumption reduction effectiveness deteriorates due to inability to gate individual buffers
Solution Approach 1:
The patent segments the clock distribution network by associating each clock buffer with its own dedicated clock gating circuit. This segmentation allows independent control of each buffer's clock signal based on specific enable signals, enabling precise power management for each logical element while maintaining overall system efficiency.
Solution Approach 2:
Each clock buffer is equipped with a dedicated clock gating circuit that applies local quality control specific to that buffer's logical element. This allows different timing and gating strategies to be applied locally to different parts of the circuit, optimizing power consumption for each segment based on its specific operational requirements.
Data Source
AI summary
A device for automatic configuration of a semiconductor integrated circuit includes a memory that stores circuit data representing a structure of a logic circuit including a first clock gating circuit, and a processor. The processor is configured to retrieve the circuit data from the memory, determine first and second logical elements from each of which an enable signal is output to the first clock gating circuit, calculate a delay time of each of the first and second logical elements, separate the first and second logical elements on the basis of the calculated delay time, and add a second clock gating circuit for the first logical element after separating the first and second logical elements.