Output-Based Clock Gating Verification Using Comparison Points
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Output-based clock gating in integrated circuits breaks combinational equivalence, making it challenging to verify functional identity between the original and clock-gated designs, especially due to the introduction of Observability Don't Care (ODC)-based clock gating conditions that complicate equivalence checking.
Innovation Solution
A method and apparatus for verifying functional equivalency between an integrated circuit design and its clock-gated counterpart using a test bench that identifies specific comparison points and injects faulty values at predetermined locations and times, leveraging ODC-based clock gating conditions to ensure that the clock-gated design matches the original design at these points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If output-based clock gating is applied to reduce dynamic switching power, then power consumption is reduced, but combinational equivalence between original and clock-gated designs is broken
Solution Approach 1:
The patent applies preliminary action by performing equivalence checking at intermediate comparison points within the combinational logic before the final output, rather than only at the end. This allows verification to be established progressively through the logic path, ensuring equivalence is maintained despite clock gating modifications. The comparison points are strategically placed to capture state values before they diverge due to clock enables.
Solution Approach 2:
The patent introduces intermediary comparison points as mediators between the original and clock-gated designs. These comparison points serve as intermediate verification checkpoints where state values are compared to ensure equivalence. The intermediaries allow the verification process to bridge the gap created by clock gating without requiring direct comparison of all final outputs.
2Loss of energy
If clock enables are added to create a clock-gated design, then dynamic switching power is reduced, but verification complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the verification process into multiple segments, each focused on a specific comparison point within the combinational logic. Rather than attempting to verify the entire design at once, the method breaks down the verification into manageable segments that can be checked independently. This segmentation reduces the apparent complexity by making the verification process modular and systematic.
Solution Approach 2:
The patent applies partial action by performing equivalence checking at selected comparison points rather than attempting to verify every possible output and intermediate signal. The method identifies critical comparison points where verification is most needed and focuses efforts there, rather than applying exhaustive verification to the entire design. This partial approach reduces verification complexity while maintaining adequate assurance of equivalence.
3Productivity
If ODC-based clock gating conditions are propagated upstream, then more clock gating opportunities are identified, but the number of unaffected comparison points for verification decreases
Solution Approach 1:
The patent applies local quality by recognizing that different regions of the design have different qualities regarding clock gating applicability. Instead of uniformly applying clock gating throughout the entire design, the method identifies specific local regions where clock gating can be applied without compromising verification. Comparison points are strategically placed in local regions that remain unaffected by ODC propagation, ensuring verification coverage is maintained in those specific locations.
Solution Approach 2:
The patent applies dimensionality change by moving the verification perspective from a single-output focus to a multi-dimensional approach that includes intermediate comparison points within the combinational logic. This adds a new dimension to verification by checking equivalence at multiple stages along the logic path, not just at the final output. This dimensional shift allows verification to succeed even when ODC propagation affects final outputs.
Data Source
AI summary
One embodiment of a method for verifying functional equivalency between a design of an integrated circuit and a corresponding clock-gated design utilizing output-based clock gating includes selecting a first one of a first plurality of internal state elements in the design and a corresponding first one of a second plurality of internal state elements in the clock-gated design, wherein an input to the first one of the first plurality of internal state elements serves as a first comparison point and an input to the corresponding first one of the second plurality of internal state elements serves as a second comparison point, and the design is to be compared against the clock-gated design at the first comparison point and the second comparison point and generating a test bench that identifies the first comparison point and the second comparison point as a set of comparison points.