Clock Generating Circuit for LED Panel Power Reduction
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Solution Overview
Problem
Conventional data driving devices for LED panels consume excessive power due to the need to constantly drive all delay units in multi-stage delay chains, even when not required, which increases power consumption.
Innovation Solution
A clock generating circuit that receives a data clock and generates a driving clock by delaying a window signal to produce sub-signals, allowing for the disabling of unnecessary delay units when the target frequency is reached, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-stage delay chain is used to generate a driving clock, then the driving clock can be generated with adjustable delay, but all delay units must be constantly driven which increases power consumption
Solution Approach 1:
The patent implements dynamic control of delay units by enabling or disabling specific stages based on the required delay amount. The controller selectively activates only the necessary delay units to achieve the target delay, rather than constantly driving all delay units in the multi-stage chain. This dynamic adaptation reduces power consumption while maintaining the ability to generate driving clocks at various frequencies.
Solution Approach 2:
The patent applies local quality by making different delay units have different operational states (enabled or disabled) based on their position in the delay chain and the required delay amount. Each delay unit can be independently controlled, allowing the system to optimize power consumption by activating only the local segments needed for the current operating condition.
2Adaptability or versatility
If all delay units are constantly driven to ensure delay adjustment capability, then frequency adjustment is flexible, but unnecessary delay units consume power
Solution Approach 1:
The system dynamically adjusts which delay units are active based on the required delay amount. The controller receives feedback about the current delay state and selectively enables or disables delay units to achieve the target delay with minimal power consumption, maintaining full adaptability while reducing energy waste from unnecessary units.
Solution Approach 2:
The patent employs partial action by activating only the minimum number of delay units necessary to achieve the required delay, rather than driving all available units. This partial activation maintains the full delay adjustment range capability while avoiding the power waste associated with driving excessive delay units that are not needed for the current operating point.
Data Source
AI summary
When the frequency of a driving clock used to drive a pixel in a display device reaches a target frequency, some of delay circuits are disabled, thereby reducing power consumption for generating the driving clock.