Clock Generating Device Dynamic Frequency Tuning
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Solution Overview
Problem
Conventional computer systems experience unnecessary power consumption due to static operating frequencies of components like the chipset and DRAM, even when idle or performing light computations, as the dynamic voltage and frequency adjustment mechanism only reduces CPU frequency and voltage without synchronously adjusting other components.
Innovation Solution
A clock generating device with a phase-locked loop (PLL) and a tuning module that adjusts the frequency of the output clock signal based on the VID of the CPU, allowing for dynamic tuning of the clock signal to match the CPU's operating mode, thereby synchronously adjusting the operating frequencies of other components and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the CPU dynamically adjusts its operating frequency and voltage according to operating mode, then the CPU's power consumption is reduced, but the chipset and DRAM maintain original frequencies causing unnecessary power consumption
Solution Approach 1:
The patent applies dynamics by making the clock generating device adjustable and adaptive. The tuning module dynamically changes the frequency dividing ratio based on CPU operating mode, allowing the system clock to transition from static to dynamic operation. This enables the chipset and DRAM frequencies to be adjusted according to actual system needs, resolving the contradiction between CPU power savings and system-wide energy consumption.
Solution Approach 2:
The patent changes the frequency parameter of the output clock signal based on CPU operating mode. By using the tuning module to adjust the frequency dividing ratio in response to VID signals from the CPU, the system dynamically modifies operating parameters (frequency and voltage) across all components, not just the CPU, thereby reducing overall system power consumption while maintaining performance requirements.
2Loss of energy
If the clock generating device dynamically tunes the output clock signal frequency according to CPU VID, then system-wide power consumption is reduced, but the device complexity increases
Solution Approach 1:
The patent implements nesting by placing the tuning module inside the existing clock generating device structure. The tuning module is integrated with the PLL and frequency divider, forming a nested configuration where the tuning functionality is contained within the existing hardware architecture. This approach reduces system-wide power consumption while minimizing the increase in device complexity by utilizing existing structural spaces.
Solution Approach 2:
The patent employs feedback by using the VID signal from the CPU to control the frequency dividing ratio through the tuning module. The system continuously monitors CPU operating mode and adjusts the clock frequency accordingly, creating a closed-loop control mechanism. This feedback-based approach enables automatic adaptation to changing system conditions, reducing power consumption without requiring complex external control systems.
3Productivity
If the frequency dividing ratio is adjusted according to CPU operating mode, then all components operate synchronously at reduced frequency, but the control mechanism becomes more complex
Solution Approach 1:
The patent applies universality by making the clock generating device serve multiple functions: it still generates the basic clock signal for the CPU and chipset, while simultaneously providing dynamic frequency tuning based on CPU operating mode. The tuning module enables the same device to handle both traditional clock generation and adaptive frequency control, allowing all components to operate synchronously at reduced frequencies without requiring separate control mechanisms for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces power consumption by dynamically tuning the clock signal frequency according to the CPU's operating mode, ensuring that all components operate efficiently and synchronously, thereby enhancing system performance and reducing energy usage.
Implementation Method 1
a phase difference between the reference clock signal and the feedback signal is detected, and the output clock signal is generated according to the phase difference
Data Source
AI summary
A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.