Clock Generating Device with Memory-Based Frequency Correlation

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Solution Overview

Problem

General-purpose electronic circuits face challenges in ensuring continuous operation when an external oscillator fails, as the clock frequency of the internal oscillator cannot be correlated with the external oscillator's frequency, especially in systems with varying specifications.

Innovation Solution

A clock generating device that stores information on the external clock signal's frequency and uses a second oscillator to generate a correlated internal clock signal, including a PLL circuit and memory to stabilize the oscillation and detect abnormalities, ensuring continuous operation even if the external oscillator fails.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If an internal oscillator is provided to generate a system clock signal when the external oscillator fails, then the electronic circuit can continue operating, but the clock frequency of the internal oscillator cannot be correlated with the external oscillator when the electronic circuit is a general-purpose product with varying specifications

Engineering Contradiction:
Improvecontinuous operation capabilityVSAvoidfrequency correlation capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent measures and stores the frequency of the external clock signal before the external oscillator may fail. By performing this frequency measurement in advance and saving it to memory, the system prepares the necessary data to later generate a correlated internal clock signal, resolving the contradiction between ensuring continuous operation and maintaining frequency correlation capability across different applications

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces memory as an intermediary element that stores the external clock signal frequency information. This stored frequency data serves as a bridge between the external and internal oscillators, enabling the internal oscillator to generate a correlated clock signal even when the external oscillator fails, thus maintaining both reliability and adaptability

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the clock frequency of the external oscillator is not predetermined, then the electronic circuit can be used in multiple systems with different specifications, but it becomes impossible to correlate the internal oscillator frequency with the external oscillator frequency when the external oscillator fails

Engineering Contradiction:
Improvemulti-system applicabilityVSAvoidfrequency correlation reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent changes the approach from using fixed predetermined frequencies to dynamically measuring and storing the actual external clock signal frequency. This parameter change enables the system to adapt to different frequency values across multiple applications while maintaining the ability to generate correlated internal clock signals, thus preserving both versatility and reliability

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution allows for stable generation of an internal clock signal correlated with the external oscillator's frequency, enabling continuous operation of electronic circuits even when the external oscillator is abnormal, without requiring predetermined clock frequencies.

Implementation Method 1

a PLL circuit that generates a second clock signal correlated with the first clock signal

Methodology Applied
Scientific EffectPhase Locked Loop (PLL):

Data Source

PatentUS10491225B2Clock generating device, electronic circuit, integrated circuit and electrical machinery
Publication Date: 2019.11.26 ROHM CO LTD
  • US10491225B2 patent drawing
  • US10491225B2 patent drawing
  • US10491225B2 patent drawing

AI summary

The present invention is related to a clock generating device for generating an internal clock signal having a frequency correlated with a clock frequency of an external oscillator when the clock frequency of the external oscillator is not specified in advance. A clock generating device 105 comprises a memory 134 and a PLL circuit 120. The memory 134 is configured to store information about a frequency of an external clock signal generated by an external oscillator 200 at a predetermined timing. The PLL circuit 120 generates a second clock signal correlated with a first clock signal based on the information stored in the memory 134.