Clock Generation Circuit Fast-Startup Standby Mode
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Solution Overview
Problem
Existing clock generation circuits for wireless modems face challenges in achieving low power consumption during standby mode while maintaining a fast start-up time to return to full operating mode, especially with the increasing demand for higher frequency operations.
Innovation Solution
The introduction of a STANDBY mode in the clock generation circuit, where a small bias current is applied to maintain internal node voltages near their operating values, allowing for a very fast start-up time of approximately 1.5 microseconds when transitioning from STANDBY to ON mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock generation circuit is completely shut down in standby mode to achieve maximum power savings, then power consumption is minimized, but the start-up time increases to conventional levels (10 microseconds)
Solution Approach 1:
The patent applies preliminary action by pre-charging internal node voltages to their target operating values before the clock generation circuit is fully activated. During standby mode, specific internal nodes are precharged to their required voltage levels, so when the circuit transitions to active mode, these nodes are already prepared and do not require full charging, thereby reducing start-up time from 10 microseconds to 1.5 microseconds while maintaining low standby power consumption.
2Loss of time
If a small bias current is applied in standby mode to pre-charge internal nodes, then start-up time is reduced to 1.5 microseconds, but power consumption during standby increases slightly
Solution Approach 1:
The patent applies local quality by selectively pre-charging only specific internal nodes that are critical for fast start-up, rather than charging all nodes in the circuit. This targeted approach ensures that the most important nodes for clock generation are ready quickly, achieving 1.5 microsecond start-up time, while minimizing the bias current required and thus keeping standby power consumption low.
Solution Approach 2:
The patent changes the voltage parameter of selected internal nodes during standby mode by applying a small bias current to maintain them at their target operating voltages. This parameter change allows the circuit to transition rapidly to full operation when needed, reducing start-up time from 10 to 1.5 microseconds, while the small bias current keeps the power penalty during standby minimal.
3Use of energy by moving object
If the clock frequency is reduced in standby mode to save power, then power consumption decreases, but the circuit cannot rapidly respond to high-performance requirements
Solution Approach 1:
The patent prepares the clock generation circuit for rapid high-performance response by pre-charging internal nodes to their target voltages during standby mode. This preliminary action ensures that when the circuit needs to transition to high-frequency operation, the internal nodes are already ready, enabling a fast 1.5 microsecond transition to full performance mode without user-perceptible delay.
Data Source
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AI summary
A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).