Clock Generation Circuit Voltage Stabilization
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Solution Overview
Problem
In semiconductor integrated circuit devices, clock generation operations over long periods lead to an increase in voltage levels, destabilizing the output and requiring additional components for high-voltage generation, which increases device area and power consumption.
Innovation Solution
The integration of an adjustment circuit within the clock generation unit, comprising series-connected PMOS transistors and a capacitor, allows for the discharge of charges on the control terminal of the first transistor to the second power supply voltage when the input clock is at a specific level, maintaining a constant voltage level and preventing voltage increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If a clock generator uses a basic power supply to generate high amplitude output clock, then the output clock amplitude is improved, but the device area and power consumption increase due to additional components
Solution Approach 1:
The adjustment circuit is integrated within the clock generation unit by sharing the control terminal of the first transistor. The series-connected PMOS transistors and capacitor are combined with the existing inverter structure, merging multiple functions into a single unified circuit block that generates high amplitude clocks without requiring separate dedicated components.
Solution Approach 2:
The first transistor's control terminal serves dual purposes: it controls the inverter operation and simultaneously serves as the charge storage node for the adjustment circuit. The basic power supply circuit is designed to be multi-functional, providing both the operating voltage and the charge pumping capability for amplitude enhancement.
2Illumination intensity
If a clock generator uses a basic power supply to generate high amplitude output clock, then the output clock amplitude is improved, but the power consumption increases
Solution Approach 1:
The adjustment circuit is integrated within the clock generation unit by sharing the control terminal of the first transistor. The series-connected PMOS transistors and capacitor are combined with the existing inverter structure, merging multiple functions into a single unified circuit block that generates high amplitude clocks without requiring separate dedicated components.
Solution Approach 2:
The first transistor's control terminal serves dual purposes: it controls the inverter operation and simultaneously serves as the charge storage node for the adjustment circuit. The basic power supply circuit is designed to be multi-functional, providing both the operating voltage and the charge pumping capability for amplitude enhancement.
3Duration of action of stationary object
If clock generation operation runs for a long period without adjustment circuit, then the operation continuity is improved, but the voltage level increases and output becomes unstable
Solution Approach 1:
The adjustment circuit operates periodically in synchronization with the clock cycles. During specific phases of the clock operation, the PMOS transistors activate to discharge accumulated charges from the control terminal, creating a periodic reset mechanism that prevents voltage drift and maintains output stability over extended operation periods.
Solution Approach 2:
The adjustment circuit provides negative feedback by detecting and correcting voltage deviations at the control terminal. When the voltage level rises during continuous operation, the charge discharge mechanism activates to bring the voltage back to the desired level, ensuring stable output clock generation over long periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration stabilizes the operation by preventing voltage level increases, reducing output variations, and minimizing the need for additional capacitors, thus enhancing micronization and decreasing power consumption.
Implementation Method 1
an adjustment circuit which forms a current path for discharging charges on the control terminal of the first transistor to the second power supply voltage when an input clock is at the first level
Implementation Method 2
a first diode circuit one end of which is connected to the first power supply voltage and the other end of which is connected to a control terminal of the first transistor
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level.