Clock Generation Control for Power Reduction
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Solution Overview
Problem
Semiconductor devices in mobile systems face challenges in completely interrupting clock generation during power-down modes due to the need to receive commands for internal operations, leading to ongoing clock generation in standby modes, which increases power consumption.
Innovation Solution
Incorporating a shifting circuit and a clock repeater that generate flags to control clock generation based on write and read signals, allowing the clock repeater to block unnecessary clock generation during specific operations, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock generation is interrupted in power-down mode to reduce power consumption, then power consumption is reduced, but the device cannot receive commands for internal operations
Solution Approach 1:
The patent segments the clock generation into different types: a first clock for internal operations and a second clock for other functions. By segmenting the clock system, the device can interrupt the second clock in power-down mode while maintaining the first clock for command reception, thus resolving the contradiction between power consumption and command reception capability.
Solution Approach 2:
The patent introduces a command decoder as an intermediary component that can receive commands using the first clock even when the second clock is interrupted. This intermediary allows the device to maintain limited functionality (command reception) while achieving power savings by disabling unnecessary clock generation for other operations.
2Adaptability or versatility
If clock generation continues in standby mode to receive commands, then command reception is maintained, but power consumption increases
Solution Approach 1:
The patent divides the clock system into a first clock for internal operations and a second clock for other functions. In standby mode, the device can maintain only the first clock for receiving commands while interrupting the second clock, thus maintaining minimal functionality while significantly reducing power consumption.
Solution Approach 2:
Instead of maintaining full clock generation in standby mode, the patent applies partial action by keeping only the essential first clock for command reception while interrupting the second clock. This partial action approach reduces power consumption while maintaining the minimum necessary functionality.
3Adaptability or versatility
If both read repeating clock and write repeating clock are generated, then all operations can be performed, but power consumption increases
Solution Approach 1:
The patent segments the repeating clocks into read repeating clock and write repeating clock, each controlled by separate shifting flags. This segmentation allows the device to generate only the necessary clock type based on the current operation, avoiding unnecessary power consumption while maintaining complete operational capability when needed.
Solution Approach 2:
The patent makes the clock generation dynamic by using shifting flags that change based on operation type. The read shifting flag and write shifting flag dynamically control which clock is generated, allowing the system to adapt its behavior based on current needs and reduce power consumption by generating only the necessary clock.
Data Source
AI summary
An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.