Clock Generation Circuit for Fast Delay Locking
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Solution Overview
Problem
Conventional delay-locked loops in semiconductor apparatuses require multiple iterations to compensate for phase differences between internal and external clocks, leading to prolonged delay locking operation times.
Innovation Solution
A clock generation circuit with a delay line, delay modeling block, phase detection block, multi-update signal generation block, and delay line control block that continuously updates the delay amount by generating phase codes and multi-update signals to synchronize internal and external clocks efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the delay-locked loop updates the delay value by operating a multitude of times to compensate for large phase difference, then the phase synchronization between internal and external clocks is achieved, but the delay locking operation time is lengthened
Solution Approach 1:
The patent applies preliminary action by performing a coarse delay adjustment before fine delay adjustment. The delay line control block first sets the delay line to a preliminary delay value based on initial phase difference detection, then performs finer adjustments. This preliminary action reduces the number of iterations needed for final synchronization, thereby shortening the overall delay locking operation time while maintaining synchronization accuracy.
2Productivity
If the conventional delay-locked loop uses a single update signal to adjust delay value, then the circuit complexity is kept simple, but the update operation cannot be performed continuously for rapid synchronization
Solution Approach 1:
The patent segments the update operation into multiple independent update signals (first update signal and second update signal) that can be generated and applied continuously. The phase detection block continuously compares phase differences and generates multiple update signals in sequence, enabling rapid iterative adjustments without requiring complex circuit reconfiguration. This segmentation allows continuous update operations that improve synchronization speed while keeping each individual update signal relatively simple.
Solution Approach 2:
The patent implements dynamics by making the delay line control block capable of receiving and responding to multiple sequential update signals. The control block dynamically adjusts the delay line value with each update signal, transitioning from a static single-update model to a dynamic multi-update model. This dynamic approach enables continuous adaptation to phase differences, significantly improving synchronization speed while the modular structure keeps circuit complexity manageable.
Data Source
AI summary
A clock generation circuit includes a delay line, a delay modeling block, a phase detection block, a multi-update signal generation block, and a delay line. The delay line delays an input clock and generates a delayed clock. The delay modeling block delays the delayed clock by a modeled delay value and generates a feedback clock. The phase detection block compares phases of the input clock and the feedback clock and generates phase information, and quantizes a phase difference between the input clock and the feedback clock and generates phase codes. The multi-update signal generation block generates a multi-update signal in response to the phase codes. The delay line control block changes a delay amount of the delay line in response to the multi-update signal and the phase information.