Clock Generation Circuit for Double Data Transfer With Lower Area
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Solution Overview
Problem
Existing clock generation circuits for double data transmission require a large area, wasting circuit resources due to the need for generating two data transmission clock signals based on one read command.
Innovation Solution
A clock generation circuit that generates N target clock signals using N clock generation sub-circuits, where odd-stage and even-stage sub-circuits perform specific logic operations on register signals and delayed clock signals to produce two groups of target clock signals, reducing the circuit area required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a generation circuit of two data transmission clock signals is used to transmit double data, then the data transmission amount is doubled, but the circuit area becomes relatively large, wasting circuit resources
Solution Approach 1:
The patent merges the generation of two groups of target clock signals into a single clock generation circuit. The circuit uses N clock generation sub-circuits (where N is an even number) that share common resources including a delayed clock signal path and logic processing units. This consolidation allows the circuit to generate multiple clock signals (doubling data transmission capability) while reducing the overall circuit area compared to having separate generation circuits for each clock signal group.
Solution Approach 2:
The clock generation circuit is designed with multi-functional sub-circuits that can generate different target clock signals through selective logic processing. Each sub-circuit can operate in different modes to produce various clock signals needed for double data transmission, making the circuit versatile and reducing the need for dedicated circuits for each function, thereby optimizing area utilization.
2Productivity
If N clock generation sub-circuits are used to generate N target clock signals, then two groups of target clock signals can be obtained, but the circuit complexity increases
Solution Approach 1:
The patent divides the clock generation function into N independent clock generation sub-circuits, where each sub-circuit is responsible for generating one target clock signal. This segmentation allows for modular design and independent optimization of each sub-circuit. The sub-circuits are organized systematically with odd-numbered and even-numbered sub-circuits using different logic processing paths, which simplifies the overall control logic while maintaining the ability to generate multiple clock signals efficiently.
Data Source
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AI summary
Embodiments of the present disclosure provide a clock generation circuit and a memory. The ith clock generation sub-circuit is configured to: perform sampling processing and latching processing on the ith register input signal based on an inverted clock signal, to generate the ith register signal; and perform first logic processing on the ith register signal and a delayed clock signal, to generate the ith target clock signal. The jth clock generation sub-circuit is configured to: perform sampling processing and latching processing on the (j-1)th register signal based on a preset clock signal, to generate the jth register signal; and perform second logic processing on the jth register signal and the delayed clock signal, to generate the jth target clock signal.