Clock Generation Circuit Duty Ratio Control Without PLL
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Solution Overview
Problem
Conventional clock generation circuits require a Phase Locked Loop (PLL) circuit to fix the duty ratio of the output clock, resulting in a large circuit scale, and there is a need for a solution that can generate an output clock with a desired duty ratio without using a PLL.
Innovation Solution
A clock generation circuit that includes a clock output circuit, first and second ramp voltage generation circuits, a comparison voltage holding circuit, and a comparator to generate an output clock with a desired duty ratio using an external clock, allowing for synchronization of level changes without the need for a PLL, utilizing capacitors and constant current circuits to control voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a PLL circuit is used to fix the duty ratio of the output clock, then the duty ratio can be fixed to a desired value, but the circuit scale becomes large
Solution Approach 1:
The patent extracts the essential function of duty ratio fixation from the complex PLL circuit and implements it using a simplified configuration consisting of a clock output circuit, ramp voltage generation circuits, comparison voltage holding circuit, and comparator. This removes unnecessary components while preserving the core functionality of generating an output clock with a fixed duty ratio independent of the external clock's duty ratio.
Solution Approach 2:
The patent changes the approach from phase-locked loop parameter control to voltage comparison parameter control. By using ramp voltages with different slopes and comparing them against a reference voltage, the circuit achieves duty ratio control through voltage parameter manipulation rather than through the complex frequency and phase parameters managed by a PLL circuit.
2Reliability
If a PLL circuit is used to generate the output clock, then the duty ratio can be fixed, but the circuit becomes large and complex
Solution Approach 1:
The patent extracts the essential function of duty ratio fixation from the complex PLL circuit and implements it using a simplified configuration consisting of a clock output circuit, ramp voltage generation circuits, comparison voltage holding circuit, and comparator. This removes unnecessary components while preserving the core functionality of generating an output clock with a fixed duty ratio independent of the external clock's duty ratio.
Solution Approach 2:
The patent implements a feedback mechanism through the comparison voltage holding circuit that stores the reference voltage and feeds it back to the comparator for continuous duty ratio verification. This ensures the output clock maintains a stable duty ratio by continuously comparing the ramp voltage against the stored reference voltage, providing reliability without requiring a full PLL circuit.
3Adaptability or versatility
If the external clock duty ratio varies, then adaptability is improved, but the output clock duty ratio becomes unstable
Solution Approach 1:
The patent introduces ramp voltage generation circuits as intermediary elements that convert the external clock signal into a standardized ramp voltage waveform. This intermediary transformation process eliminates the influence of the external clock's duty ratio variations, allowing the comparator to generate an output clock with a stable, fixed duty ratio regardless of the input clock's duty ratio changes.
Solution Approach 2:
The patent replaces the direct electrical signal transmission approach with a voltage transformation mechanism. Instead of directly using the external clock signal, the system transforms it into a ramp voltage through capacitive integration, then uses voltage comparison to generate the final output clock. This substitution of the signal processing mechanism ensures duty ratio stability independent of the external clock characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution enables the generation of an output clock with a desired duty ratio in a compact circuit scale, suitable for switching power supply devices and semiconductor devices, independent of the external clock's duty ratio, reducing circuit complexity and size.
Implementation Method 1
a first ramp voltage generation circuit arranged to generate a first ramp voltage whose voltage value changes with a period of interval between neighboring predetermined level changes of the target clock
Implementation Method 2
a second ramp voltage generation circuit arranged to generate a second ramp voltage whose voltage value changes with a period of the interval
Implementation Method 3
a comparator arranged to compare the first ramp voltage with the comparison voltage
Data Source
AI summary
A clock generation circuit, which generates an output clock using an external clock as a target clock, includes a circuit arranged to change the output clock to high level in synchronization with an up edge of the target clock, circuits arranged to generate first and second ramp voltages with a period of interval between neighboring up edges of the target clock, and a circuit arranged to hold a comparison voltage corresponding to a second ramp voltage when an up edge of the target clock occurs. The level of the output clock is changed from high level to low level based on a comparison result between the first ramp voltage and the comparison voltage.