Clock Generation Device with Dynamic Frequency Tuning
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Solution Overview
Problem
Conventional internal clock signal generation circuits in semiconductor memory devices cannot adjust the clock signal to a target frequency due to changes in process, voltage, and temperature (PVT), making it difficult to perform accurate testing using stand-alone-machine based test devices or Built-In Self Test (BIST) circuits.
Innovation Solution
A clock generation device that includes an oscillator to tune the internal clock signal in response to a tuning signal, a counter to count the internal clock, and a comparator to compare the count signal with a target count signal, allowing the oscillator to adjust the internal clock period by increasing, decreasing, or fixing it to match the target frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional internal clock signal generation circuit is used, then the circuit structure is simple, but the clock signal cannot be adjusted to a target frequency due to PVT changes
Solution Approach 1:
The patent implements dynamic frequency adjustment by introducing a frequency tuning mechanism that can modify the internal clock signal in real-time. The frequency tuning circuit receives the internal clock signal and adjusts its frequency based on feedback from a frequency detector, enabling the system to adapt to PVT changes dynamically rather than being fixed at a predetermined frequency.
Solution Approach 2:
The patent employs a feedback control mechanism where a frequency detector continuously monitors the actual frequency of the internal clock signal and feeds this information back to the frequency tuning circuit. This closed-loop feedback system automatically adjusts the clock frequency to match the target frequency, resolving the contradiction between simplicity and adaptability.
2Measurement precision
If stand-alone-machine based test devices are used, then the testing equipment is external and separate, but the memory device cannot be tested accurately due to inability to adjust internal clock frequency
Solution Approach 1:
The patent implements Built-In Self Test (BIST) functionality where the memory device tests itself using an integrated test controller and test logic. The BIST mechanism generates test patterns, executes them through the memory array, and detects errors autonomously, eliminating the need for complex external test equipment while ensuring accurate testing even under varying PVT conditions.
3Extent of automation
If BIST circuit is included in the semiconductor device, then the test functionality is integrated, but the testing becomes incorrect due to oscillator errors under PVT changes
Solution Approach 1:
The patent ensures test reliability by implementing dynamic frequency adjustment specifically for the BIST operation. The frequency tuning circuit adjusts the internal clock frequency to a predetermined target frequency before and during BIST testing, ensuring that the test operations are performed at the correct frequency regardless of PVT variations, thus maintaining high test correctness.
4Adaptability or versatility
If the oscillator period is fixed, then the circuit is simple, but the internal clock cannot be tuned to the target frequency under PVT changes
Solution Approach 1:
The patent transforms the fixed oscillator into a dynamic frequency-tunable oscillator. The frequency tuning circuit receives control signals that adjust the oscillator's output frequency in real-time. This dynamic adjustment capability allows the internal clock to be tuned to the target frequency even when process, voltage, or temperature conditions change, resolving the contradiction between simplicity and adaptability.
Data Source
AI summary
A clock generation device and a semiconductor device including the same are disclosed, which may tune an internal clock to a desired frequency. The clock generation device may include an oscillator configured to tune an oscillation signal in response to a tuning signal, and adjust a period of an internal clock. The clock generation device may include a counter configured to count the internal clock in response to a count enable signal, and output a count signal. The clock generation device may include a comparator configured to compare the count signal with a test count signal including a target count number of the internal clock, and output the tuning signal.