Clock Generation Circuit Control via Interrupt Masking
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Solution Overview
Problem
Existing control systems for clock generation circuits in computer systems cannot effectively shorten the operation time of clock generation circuits and enable interrupt signal transmission on peripheral buses that lack the automatic bus clock stop function, leading to reduced lifespan and impaired responsiveness.
Innovation Solution
A control apparatus with a timer that alternately stops and restarts the clock generation circuit based on measured time intervals, using an interrupt mask to manage interrupt signals during clock stop and restart operations, allowing for efficient clock generation circuit operation and interrupt signal transmission even without automatic bus clock stop functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If the bus clock is stopped to extend the lifespan of the clock generation circuit, then the operation time of the circuit is reduced, but interrupt signal transmission becomes impossible
Solution Approach 1:
The system performs preliminary actions by saving the interrupt request status and pending interrupt information before stopping the bus clock. This allows the system to maintain interrupt functionality across clock stop/start cycles by restoring the interrupt state after the clock is restarted, thus resolving the contradiction between reducing clock operation time and maintaining interrupt signal transmission capability
Solution Approach 2:
The CPU acts as an intermediary between the interrupt controller and the peripheral devices during clock stop periods. By handling interrupt requests through software polling or status checking mechanisms when the bus clock is stopped, the system maintains interrupt functionality without requiring the bus clock to remain active, thus extending clock generation circuit lifespan while preserving interrupt capability
2Reliability
If the bus clock is continuously supplied to ensure interrupt signal transmission, then interrupt responsiveness is maintained, but the operation time of the clock generation circuit increases
Solution Approach 1:
The system implements periodic clock stopping and restarting based on detected bus idle periods. By alternating between clock stop and start operations during idle times while maintaining interrupt handling capability through the CPU, the system reduces overall clock generation circuit operation time while ensuring interrupt signals can be transmitted when needed
Solution Approach 2:
The system uses the CPU's own processing capabilities to handle interrupt detection and management during bus clock stop periods. Instead of relying on continuous bus clock operation for interrupt transmission, the CPU independently manages interrupt status checking and response, allowing the bus clock to be stopped during idle periods thus reducing clock generation circuit operation time
3Device complexity
If a bus without automatic bus clock stop function is used to reduce device complexity, then manufacturing cost is reduced, but the ability to shorten clock operation time is lost
Solution Approach 1:
The CPU is given multiple functions: it not only executes normal processing tasks but also performs bus idle detection, interrupt status management, and clock control decisions. This multi-functionality allows the system to achieve automatic bus clock stop capability using a simple bus without adding complex dedicated hardware, thus reducing device complexity while maintaining the ability to shorten clock operation time
Solution Approach 2:
The system merges the clock control function with the existing CPU and bus interface components. Instead of adding a separate automatic clock stop circuit, the clock stop/start control is integrated into the CPU's existing control logic and bus arbitration mechanisms, thereby achieving clock operation time reduction without increasing bus function complexity or manufacturing cost
Data Source
AI summary
The present control apparatus includes a timer for measuring a predetermined time and a clock generation circuit for supplying a clock to a peripheral device. Furthermore, the control apparatus includes a CPU for alternatingly stopping and restarting driving of the clock generation circuit based on the measuring of the predetermined time performed by the timer. On the other hand, the peripheral device includes an interrupt mask that restricts output of an interrupt signal to the control apparatus via the peripheral bus. When the driving of the clock generation circuit is to be stopped, the control apparatus sets the interrupt mask, and when the driving of the clock generation circuit is to be restarted, the control apparatus cancels the interrupt mask.