Clock Generation Circuit for Dual-Data Memory With Shared Logic Stages
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Solution Overview
Problem
Existing clock generation circuits for double data transmission require a large area, wasting circuit resources due to the need for generating two data transmission clock signals based on a single read command.
Innovation Solution
A clock generation circuit that includes N clock generation sub-circuits, where odd-stage sub-circuits perform OR logic processing and even-stage sub-circuits perform NAND logic processing to generate two groups of target clock signals, reducing the need for duplicate clock signal generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock generation circuits are used for each data transmission clock signal, then the reliability of clock signal generation is improved, but the circuit area and resource consumption increase significantly
Solution Approach 1:
The patent merges the functionality of multiple clock generation circuits into a single unified circuit. The clock generation circuit uses shared components including an initial register, delay register, and logic gate units that can dynamically generate multiple clock signals (CLK0, CLK1, CLK2, CLK3) through configurable logic operations, thereby reducing overall circuit area while maintaining signal generation reliability
Solution Approach 2:
The clock generation circuit is designed with multi-functionality to generate different clock signals based on different data transmission modes. By configuring the logic gate units and register connections differently, the same circuit can operate in single data mode (generating one clock signal) or double data mode (generating multiple clock signals), making the circuit adaptable to various transmission requirements without requiring separate dedicated circuits
2Productivity
If duplicate clock signal generation circuits are implemented, then the productivity of data transmission is improved, but the circuit resource consumption increases
Solution Approach 1:
The clock generation circuit employs dynamic configuration where the logic gate units can be selectively enabled or disabled based on the required data transmission mode. In double data transmission mode, all logic units are activated to generate multiple clock signals simultaneously, maximizing productivity. In single data mode, only the necessary logic units are active, conserving circuit resources. This dynamic adaptability allows the circuit to optimize resource usage according to actual transmission needs
Solution Approach 2:
The clock generation circuit is divided into multiple independent logic gate units (first logic gate unit, second logic gate unit, etc.), each capable of generating specific clock signals. These segmented units can be selectively activated based on transmission requirements, allowing the circuit to allocate resources efficiently - activating only the necessary segments for the current operation rather than running all segments continuously
3Device complexity
If a single clock generation circuit generates multiple clock signals, then the circuit resource efficiency is improved, but the device complexity increases
Solution Approach 1:
The circuit manages complexity by changing operational parameters (which logic units are active, register connection configurations) rather than changing the physical structure. The same physical circuit components can be reconfigured through parameter changes to generate different clock signals, avoiding the need for multiple physical circuits while maintaining resource efficiency
Data Source
AI summary
Embodiments of the present disclosure provide a clock generation circuit and a memory. The ith clock generation sub-circuit is configured to: perform sampling processing and latching processing on the ith register input signal based on an inverted clock signal, to generate the ith register signal; and perform first logic processing on the ith register signal and a delayed clock signal, to generate the ith target clock signal. The jth clock generation sub-circuit is configured to: perform sampling processing and latching processing on the (j-1)th register signal based on a preset clock signal, to generate the jth register signal; and perform second logic processing on the jth register signal and the delayed clock signal, to generate the jth target clock signal.