Clock Generation Device Reducing Spurious Components
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Solution Overview
Problem
Existing clock generation devices, such as those using phase-locked loops and delay-locked loops, often produce clock signals with spurious components, making it difficult to synchronize clock signals and data, especially as data transfer frequencies increase and bus loads rise.
Innovation Solution
A clock generation device comprising a delay line, pulse generator, and clock generator that modulates a reference clock signal by multiplying its period by a numerical value selected from a set according to a certain probability, generating a pulse signal and subsequently a clock signal with a distinct period, thereby reducing spurious components and improving synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop or delay-locked loop is used to synchronize the clock signal and data, then the clock signal can be maintained, but spurious components are generated that make it difficult to synchronize the clock signal and data
Solution Approach 1:
The delay line is divided into multiple delay elements connected in series, each contributing a portion of the total delay. This segmentation allows precise control of the delay amount while distributing the spurious component generation across multiple stages, reducing their overall impact on the clock signal quality.
Solution Approach 2:
The delay amount is dynamically adjusted based on the period of the input clock signal. The delay line is configured to provide a delay corresponding to a fractional multiple of the input clock period, allowing the system to adapt to different clock frequencies and maintain optimal synchronization while minimizing spurious components.
2Productivity
If the data transfer frequency is increased and bus load increases, then data transfer efficiency is improved, but the timing to synchronize the clock signal and data becomes more critical and difficult
Solution Approach 1:
The system uses feedback from the phase detector to adjust the delay line configuration. The phase detector monitors the synchronization between the delayed clock signal and the data signal, and this information is fed back to optimize the delay amount, ensuring precise timing alignment even at high data transfer frequencies.
Solution Approach 2:
The delay amount is changed as a variable parameter based on the input clock period. By expressing the delay as a fractional multiple of the input clock period (e.g., 0.5T, 0.75T), the system can dynamically adjust the delay parameter to match different operating conditions and maintain precise synchronization timing.
Data Source
AI summary
A clock generation device includes a delay line that generates a modulated clock signal from a reference clock signal having a first period, a pulse generator configured to receive the modulated clock signal and generate a pulse signal in response to edges of pulses included in the modulated clock signal, and a clock generator that generates a clock signal having a second period distinguished from the first period, based on the reference clock signal and the pulse signal. The delay line generates a first pulse based on the reference clock signal and then generates a second pulse after a time modulated from the first period by a result of multiplying the second period by a first numerical value selected from a plurality of numerical values according to a certain probability.