Clock Generation Apparatus Synchronization Control

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Solution Overview

Problem

In multiplexed clock generation systems, synchronization between circuits is often lost due to differences in path length and oscillator frequency characteristics, leading to incorrect clock recognition and synchronization failures during clock switching.

Innovation Solution

A clock generation apparatus with a clock determination unit that assesses the cycle shift time between two clock signals and a clock switching unit that switches the signals based on predetermined conditions, ensuring synchronization is maintained by preventing unnecessary clock generation during circuit switching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If clock switching is performed when phases are aligned, then switching timing is simplified, but short pulses occur causing synchronization loss in reception circuits

Engineering Contradiction:
Improveclock switching timingVSAvoidsynchronization between circuits
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The system performs preliminary phase adjustment of the stand-by system clock to create a predetermined phase difference before switching occurs. This advance preparation prevents short pulse generation during switching by ensuring that when the active system clock switches to the stand-by system clock, the phase transition is smooth and controlled, eliminating the synchronization loss that would otherwise occur in reception circuits with path differences.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If separate oscillators are used for active and stand-by clocks, then multiplexing reliability is improved, but frequency characteristic differences cause phase shifts

Engineering Contradiction:
Improvemultiplexing system reliabilityVSAvoidphase relationship between clocks
Core Design Contradiction:
ReliabilityVSStability of the object's composition

Solution Approach 1:

The system continuously monitors the phase difference between the active system clock and stand-by system clock, and dynamically adjusts the stand-by system clock's phase to maintain a predetermined relationship. This feedback mechanism compensates for frequency characteristic differences between separate oscillators, ensuring that when switching occurs, the phase relationship is controlled and short pulses are prevented, thereby maintaining synchronization across all reception circuits.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If path length differences are accommodated, then all reception circuits can be supported, but synchronization loss occurs due to pulse recognition differences

Engineering Contradiction:
Improvereception circuit supportVSAvoidclock synchronization
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The system applies preliminary anti-action by creating a controlled phase difference before switching that specifically counteracts the problematic effect of path length differences. By ensuring that the stand-by system clock is phase-adjusted in advance, the system prevents the generation of short pulses that would be differentially recognized by reception circuits with different path lengths, thereby maintaining synchronization across all circuits regardless of their path length variations.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS9654277B2Clock generation apparatus, server system and clock control method
Publication Date: 2017.05.16 CLOUD BYTE LLC
  • US9654277B2 patent drawing
  • US9654277B2 patent drawing
  • US9654277B2 patent drawing

AI summary

In order to provide a multiplexed clock generation apparatus in which synchronization between circuits based on a received clock is not lost, a clock generation apparatus is made to have a clock determination unit which determines whether a cycle shift time between a first clock signal and a second clock signal satisfies a predetermined condition or not and a clock switching unit which switches the first clock signal and the second clock signal based on determination of the clock determination unit. The clock determination unit determines that clock switching is possible when, as the predetermined condition, a first condition that a cycle shift time is equal to or more than a period from a setup start time to a hold end time of a signal specified for a clock bus and a second condition that the cycle shift time exists before the next setup start time are satisfied together.