Multi-Stage Clock Generation for Synchronized Internal Clock Edges
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Solution Overview
Problem
As the operating speed of computer systems increases, generating internal clock signals with lower frequencies from high-frequency system clock signals becomes challenging, requiring efficient clock division circuits to ensure stable operation.
Innovation Solution
The proposed clock generating circuit includes a first division circuit, an internal circuit, a second division circuit, and an enable control circuit. The first division circuit generates a first group of internal clock signals by dividing the clock signal, while the internal circuit generates a delayed clock signal based on an enable signal. The second division circuit then generates a second group of internal clock signals by dividing the delayed clock signal, with the enable control circuit generating the enable signal based on one of the first group of internal clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the frequency of the system clock signal is increased to improve operating speed, then productivity increases, but generating stable internal clock signals becomes more difficult and reliability deteriorates
Solution Approach 1:
The clock division process is segmented into multiple stages: a first division circuit divides the high-frequency system clock signal into a first internal clock signal, and a second division circuit divides the first internal clock signal into a second internal clock signal. This multi-stage segmentation allows stable internal clock generation even when the system clock frequency is increased for higher operating speed.
2Device complexity
If a single clock division circuit is used to generate internal clock signals, then device complexity is reduced, but synchronization accuracy between different clock edges deteriorates
Solution Approach 1:
The clock division function is segmented across multiple circuits: a first division circuit generates a first internal clock signal from the system clock signal, and a second division circuit generates a second internal clock signal from the first internal clock signal. This segmentation enables precise synchronization control for different clock edges (rising and falling) while maintaining manageable device complexity through modular design.
Solution Approach 2:
The first internal clock signal acts as an intermediary between the system clock signal and the second internal clock signal. This intermediary signal enables the second division circuit to achieve accurate synchronization by dividing the already-divided first internal clock signal, rather than directly dividing the high-frequency system clock signal.
3Device complexity
If clock signals are divided in a single stage, then device complexity is reduced, but manufacturing precision of synchronized clock edges deteriorates
Solution Approach 1:
The clock division structure is segmented into multiple stages with the first division circuit producing a first internal clock signal and the second division circuit producing a second internal clock signal. This segmented structure achieves precise manufacturing-level synchronization for different clock edges by distributing the division function across multiple circuits rather than using a single complex circuit.
Data Source
AI summary
A clock generating circuit includes a first division circuit and a second division circuit. The first division circuit is configured to generate a first group of internal clock signals by dividing a clock signal. The second division circuit is configured to generate a second group of internal clock signals by dividing a delayed clock signal, the delayed clock signal generated by an internal circuit delaying the clock signal. An operation timing of the second division circuit can be adjusted based on one of the first group of internal clock signals generated by the first division circuit.