Clock Generation Circuit Test Coverage

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Solution Overview

Problem

Conventional clock divider circuits in integrated circuits face challenges with increased clock latency and inadequate test coverage due to complex test circuitry, which complicates design and power consumption, especially in scan testing modes.

Innovation Solution

A clock generation circuit with first and second latches and a selector, where a logic gate generates a selector control signal to choose between an input clock signal and a divided clock signal, eliminating the need for additional selectors and reducing test clock multiplexing, thereby simplifying clock balancing and enhancing test coverage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple selectors and multiplexers are used to differentiate between functional clocks and test clocks, then test coverage is improved, but clock latency and device complexity increase

Engineering Contradiction:

Improvetest coverageVSAvoidclock latency

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the functional clock path and test clock path by using a single selector circuit that can operate in different modes. Instead of having separate selectors for functional and test operations, the invention uses one selector that is controlled by a mode signal to either pass the functional clock or the test clock, thereby reducing the number of components and simplifying the clock distribution network.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The selector circuit is designed to be multi-functional, serving both functional clock distribution and test clock distribution purposes. By controlling the selector with a mode signal, the same hardware infrastructure can accommodate both operational modes, eliminating the need for dedicated test clock multiplexing circuits and reducing overall device complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple selectors and multiplexers are used to differentiate between functional clocks and test clocks, then test coverage is improved, but power consumption increases

Engineering Contradiction:

Improvetest coverageVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

3Reliability

If test clock multiplexing is implemented through multiple selectors, then test coverage is improved, but design complexity and clock balancing difficulty increase

Engineering Contradiction:

Improvetest coverageVSAvoiddesign complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Ease of operation

If conventional clock divider circuits with multiple buffers and selectors are used, then clock signal distribution is achieved, but test coverage of the clock generation logic is inadequate

Engineering Contradiction:

Improveclock signal distributionVSAvoidtest coverage

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The clock generation circuit is designed to be self-testable by incorporating scan chain integration directly into the clock divider logic. The circuit uses its own internal signals and structures to enable testing, eliminating the need for external test equipment or complex test arrangements. The scan chain allows test patterns to be loaded and propagated through the clock generation logic to verify its operation.

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS7421610B2Clock generation circuit

Publication Date: 2008.09.02 NXP USA INC

AI summary

A clock generation circuit for an integrated circuit device, such as an SOC, has increased test coverage. The clock generation circuit includes first and second latches that receive an input clock signal at their clock inputs and a selector that receives at first and second data inputs respectively, the input clock signal and an output of the second latch circuit, which is a divided clock signal. A logic gate has a first input connected to an output of the first latch and a second input that receives a scan mode signal. The logic gate generates a selector control signal provided to the selector.