Clock Signal Generator with Pulse-Counted Bias Current Reduction
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Solution Overview
Problem
Existing clock signal generators face challenges in reducing current consumption while stabilizing the output of clock signals early, leading to potential device malfunctions due to 'clock omission' and amplitude decrease.
Innovation Solution
A clock signal generator that includes a crystal oscillator, amplification oscillation signal generation, clock pulse counting, and constant current reduction mechanisms to amplify the oscillation signal and switch the clock signal source based on pulse counting, ensuring stable output with reduced bias current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If current consumption for generating the clock signal is reduced, then power efficiency is improved, but the amplitude of the clock signal decreases causing clock omission and potential device malfunction
Solution Approach 1:
The system performs preliminary action by using a self-oscillator to generate a clock signal during the warm-up period before the crystal oscillator circuit is fully operational. This preliminary clock signal ensures the CPU can execute instructions without malfunction while the crystal oscillator is stabilizing, preventing device malfunction during the transition period.
Solution Approach 2:
A pulse counter is introduced as an intermediary component to monitor the stability of the crystal oscillator circuit. The pulse counter counts clock pulses from the crystal oscillator and compares the count against a reference value to determine when the oscillation has stabilized. This intermediary mechanism enables automatic switching between the self-oscillator and crystal oscillator based on measured stability, ensuring reliable clock signal transition.
2Loss of time
If the clock signal is outputted stably as early as possible using a self-oscillator, then the period until stable clock output is reduced, but the device complexity increases due to additional switching mechanisms
Solution Approach 1:
The patent merges the self-oscillator and crystal oscillator circuits into a unified oscillation control system with automatic switching capability. The pulse counter integrates with both oscillators to monitor the crystal oscillator's stability and automatically control the switching timing. This merged design reduces the period until stable clock output by eliminating manual configuration while keeping the circuit complexity manageable through integrated control logic.
Solution Approach 2:
The oscillation control circuit performs self-service by automatically monitoring its own operational state through the pulse counter and autonomously switching between oscillators based on the stability of the crystal oscillator. The system uses internal feedback from the pulse count comparison to control the switching transistor, eliminating the need for external control mechanisms and reducing overall system complexity.
3Reliability
If the amplitude of the amplification oscillation signal is increased to prevent clock omission, then signal reliability is improved, but current consumption increases
Solution Approach 1:
The system implements periodic action by operating in distinct phases: a warm-up period where the self-oscillator provides the clock signal, and a stable operation period where the crystal oscillator provides the clock signal. During the stable operation period, the amplification oscillation signal is maintained at sufficient amplitude to prevent clock omission. This periodic structure allows the system to achieve reliable clock output only when necessary, reducing overall current consumption compared to continuously maintaining high amplitude.
Data Source
AI summary
The present invention provides a clock signal generator capable of reducing current consumption and stably outputting a clock signal early. When it is discriminated that the amplitude of an amplification oscillation signal obtained by amplifying an oscillation signal produced from a crystal oscillator according to a constant current value has exceeded threshold amplitude, the clock signal generator generates a clock signal, based on the amplification oscillation signal. When it is discriminated that the total number of clock pulses of the clock signal has exceeded a predetermined pulse number, the clock signal generator reduces the constant current value.