Clock Generator Layout for Black Frame Insertion in Displays
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Solution Overview
Problem
Display devices experience motion blur due to overlapping afterimages when displaying moving images, and as resolution and driving frequency increase, the number of level shifters and input signals required for black frame insertion technology increases, leading to complexity and inefficiency.
Innovation Solution
A display device with a clock generator that generates clock signals with different phases and integrates black frame insertion by using a clock generator that autonomously generates multiple clock signals with varying phases, reducing the need for individual level shifters and input signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If multiple level shifters are used to generate clock signals for black frame insertion, then motion blur is reduced, but device complexity increases
Solution Approach 1:
The patent combines multiple level shifter functions into a single level shifter by integrating a clock generator that produces multiple phase-shifted clock signals internally. This merging approach maintains the motion blur reduction capability while eliminating the need for multiple separate level shifters and their associated input signals, directly resolving the technical contradiction between harmful factor reduction and device complexity.
Solution Approach 2:
The single level shifter in the patent is designed to perform multiple functions by receiving a single input clock signal and generating multiple phase-shifted clock signals through an integrated clock generator. This multi-functionality allows the system to achieve black frame insertion for multiple pixel line groups without requiring multiple dedicated level shifters, thereby reducing device complexity while maintaining motion blur reduction effectiveness.
2Adaptability or versatility
If multiple level shifters are used to generate clock signals, then black frame insertion capability is improved, but the number of input signals and control lines increases
Solution Approach 1:
The patent merges the input signal requirements of multiple level shifters into a single input signal by using an integrated clock generator within one level shifter. The clock generator internally produces multiple phase-shifted clock signals from a single input clock signal, eliminating the need for multiple separate input signals and control lines while maintaining full black frame insertion capability across all pixel line groups.
Solution Approach 2:
The level shifter performs self-service by incorporating a clock generator that autonomously generates multiple phase-shifted clock signals from its own input clock signal. This self-service mechanism eliminates the need for external control lines and additional input signals that would otherwise be required to coordinate multiple separate level shifters, thereby reducing device complexity while preserving adaptability.
3Measurement precision
If resolution and driving frequency are increased, then display quality is improved, but the number of level shifters and input signals required increases
Solution Approach 1:
The patent applies merging by consolidating multiple level shifter functions into a single integrated unit with an internal clock generator. This allows the system to support high resolution and driving frequency requirements without proportionally increasing the number of level shifters and input signals, as the single level shifter can handle multiple pixel line groups through its internally generated phase-shifted clock signals.
Data Source
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AI summary
Described is a display device which includes a display unit including gate lines and pixels electrically coupled to the gate lines; a timing controller configured to generate an on-clock signal, an off-clock signal, an enable signal, and a common signal; a clock generator configured to generate a plurality of clock signals having different phases based on the on-clock signal and the off-clock signal, when the enable signal has a first voltage level, wherein the clock generator is to insert a common pulse into each of the plurality of clock signals based on the common signal, when the enable signal has a second voltage level different from the first voltage level; and a gate driver configured to generate gate signals based on the plurality of clock signals, and to sequentially provide the gate signals to the gate lines.