Clock Generator Adjusting Frequency for Buffer Fill in Playback

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Solution Overview

Problem

Existing data synchronized playback systems face interruptions or cutoffs when unable to synchronize with the transmitting side due to clock frequency mismatches, particularly in hardware-limited scenarios or when using software-based AV decoders, leading to performance changes in the overall apparatus.

Innovation Solution

A data synchronized playback apparatus that includes a buffer, a buffer fill measurement unit, a decoder, and a clock generator, which adjusts the clock frequency based on the measured data quantity in the buffer to maintain continuous playback of audio and video data without requiring a PLL circuit, thus preventing performance changes even in software-based AV decoders.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a PLL circuit is used to synchronize clock frequencies, then data synchronization is improved, but device complexity increases

Engineering Contradiction:
Improvedata synchronizationVSAvoidPLL circuit
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts the essential function of clock frequency synchronization from the complex PLL circuit and implements it through a simpler buffer-fill-based control mechanism. The system monitors buffer fill levels and adjusts playback speed accordingly, eliminating the need for hardware PLL circuits while maintaining synchronization reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention replaces the mechanical/electronic PLL circuit with a software-based buffer management system. By using buffer fill measurement and digital clock adjustment, the system achieves clock synchronization without requiring dedicated hardware PLL components, thereby reducing device complexity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Duration of action of moving object

If clock frequency is adjusted to prevent buffer overflow/underflow, then continuous playback is improved, but apparatus performance changes

Engineering Contradiction:
Improvecontinuous playbackVSAvoidapparatus performance
Core Design Contradiction:
Duration of action of moving objectVSReliability

Solution Approach 1:

The invention applies local quality by adjusting the clock frequency specifically for the audio playback path rather than for the entire apparatus. The clock generator modifies only the audio clock based on buffer fill levels, while other system operations continue at their original speed, thus maintaining continuous playback without degrading overall apparatus performance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention segments the clock generation into separate paths: a system clock for general apparatus operation and an audio clock for playback. This segmentation allows independent adjustment of the audio clock based on buffer conditions without affecting other system functions, resolving the contradiction between continuous playback and performance stability.

Inventive Principle:
Principle #1Segmentation

3Reliability

If buffer fill measurement is performed continuously, then playback synchronization is improved, but processing load increases

Engineering Contradiction:
Improveplayback synchronizationVSAvoidprocessing load
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention implements periodic action by measuring buffer fill at specific intervals rather than continuously. The buffer fill measurement unit samples the buffer status at predetermined times, providing sufficient synchronization information while minimizing processing load. This periodic sampling approach maintains playback synchronization without excessive computational overhead.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS7639706B2Data synchronized playback apparatus
Publication Date: 2009.12.29 MAXELL LTD
  • US7639706B2 patent drawing
  • US7639706B2 patent drawing
  • US7639706B2 patent drawing

AI summary

A data synchronized playback apparatus comprises a buffer which stores streaming data, a buffer fill quantity measurement unit which measures the amount of streaming data stored in the buffer, a decoder which decodes the streaming data and sends decoded data to a D/A converter, a D/A converter which converts the decoded data to an analog signal, a clock generator which generates a clock signal with a frequency that changes according to the measured data quantity, and the digital/analog converter operates based on the clock signal generated by the clock generator.