Clock Generator Circuit Abnormal Waveform Detection
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Solution Overview
Problem
Semiconductor integrated circuits with phase locked loop (PLL) circuits face issues with distorted clock waveforms due to jitter or fluctuations in the voltage controlled oscillator (VCO) supply voltage, leading to potential faulty operations in other function circuits.
Innovation Solution
A clock generator circuit that includes a PLL circuit, a selector, a selector signal generator circuit for detecting abnormal waveforms, and a delay circuit to prevent abnormal waveforms from propagating to subsequent function circuits by switching to a stable clock source when an abnormality is detected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a PLL circuit is used to generate high-frequency clocks, then frequency multiplication capability is improved, but clock waveform distortion occurs due to VCO supply voltage fluctuations
Solution Approach 1:
A delay circuit is introduced as an intermediary component between the PLL circuit and the selector. This delay circuit delays the second clock signal so that even if an abnormal waveform pulse is detected, the selector can switch to the first clock signal before the abnormal pulse reaches the downstream circuits, thus preventing faulty operations
Solution Approach 2:
The delay circuit performs preliminary action by delaying the abnormal clock signal before it can affect downstream circuits. The delay time is specifically designed to be longer than the switching response time, ensuring that the selector can complete its switching operation before the abnormal pulse propagates further
2Reliability
If a selector switches clock sources rapidly in response to abnormal waveforms, then faulty operations are prevented, but timing accuracy may be compromised
Solution Approach 1:
The delay circuit performs preliminary action by delaying the abnormal clock signal before it can affect downstream circuits. The delay time is specifically designed to be longer than the switching response time, ensuring that the selector can complete its switching operation before the abnormal pulse propagates further
Solution Approach 2:
The selector signal generator circuit continuously monitors the second clock waveform and provides feedback to the selector. When an abnormal waveform is detected, the feedback signal triggers the selector to switch to the first clock signal, creating a closed-loop control system that maintains timing accuracy while preventing faulty operations
Data Source
AI summary
A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.