Clock Generator Configuration Sequencing for Faster Power-Up
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Solution Overview
Problem
Traditional methods for reconfiguring integrated circuits using electrical programming result in inefficient nonvolatile memory structures due to distributed storage of configuration data, leading to prolonged power-up times for clock generators and other circuit elements.
Innovation Solution
A novel architecture that sequentially transfers configuration data from nonvolatile memory to volatile memory during power-up, allowing clock elements to initiate operation quickly by positioning early download sequences and enabling parallel lock acquisition with ongoing download sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If configuration data is stored in distributed nonvolatile memory locations throughout the semiconductor die, then every bit can be supported in proximity to respective die locations, but the nonvolatile memory structure becomes inefficient and power-up time increases
Solution Approach 1:
The patent consolidates distributed nonvolatile memory locations into a centralized nonvolatile memory array. Instead of having configuration bits scattered throughout the semiconductor die at various clock element locations, all configuration data is stored in a single centralized array, which is then downloaded to volatile memory during power-up.
Solution Approach 2:
The patent implements a download sequence that transfers configuration data from nonvolatile memory to volatile memory before clock elements are activated. By positioning the download sequence to load configuration data into volatile memory in advance, clock elements can immediately use the pre-loaded data without waiting for configuration during operation.
2Productivity
If configuration data is transferred sequentially from nonvolatile memory to volatile memory, then memory structure efficiency improves, but clock elements may experience delays in reaching stable operation
Solution Approach 1:
The patent positions the download sequence to load configuration data for clock elements into volatile memory before those elements are activated. This preliminary loading ensures that when clock elements become operational, their configuration data is already available in volatile memory, eliminating configuration delays and enabling immediate stable operation.
Solution Approach 2:
The patent maintains continuous download sequencing from nonvolatile to volatile memory while clock elements are being activated. The download sequence operates continuously, ensuring that configuration data is always being transferred and made available, which supports uninterrupted clock element initialization and reduces overall time to stable operation.
3Loss of time
If early download sequence positioning is used to allow clock elements to commence operation quickly, then power-up time reduces, but configuration of other clock elements may be impacted
Solution Approach 1:
The patent positions the download sequence to load configuration data for certain clock elements into volatile memory before those elements are activated, allowing them to operate immediately with pre-loaded configuration. This preliminary action reduces power-up time for those specific elements without compromising the overall configuration process.
Solution Approach 2:
The patent maintains continuous download sequencing that operates throughout the power-up process. While some clock elements can operate with early-loaded configuration data, the download sequence continues uninterrupted to configure remaining clock elements, ensuring complete and reliable configuration of all elements by the end of the power-up sequence.
Data Source
AI summary
Methods, systems, and devices are described for the implementation of a novel architecture to support download sequencing techniques for circuit configuration data. Sets of configuration data from nonvolatile memory may be sequentially transferred to volatile memory to support reconfigurable circuit elements, for example, for use in a clock generator. Different programmable circuit elements may use configuration data, but have different ramp-up times before stable operation. With early download sequence positioning of configuration data, and corresponding immediacy in initiation of operation, certain clock elements are able to commence initiation of operation while remaining clock elements are provided with configuration data from a latter portion of the download sequence.