Clock Signal Generator Using Dual Delay Lines for Fine Timing Resolution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock signal generators have limited period resolution due to constraints on the number of logic gates and require time-consuming calibration for fine delay circuits, making it difficult to achieve high resolution and self-calibration.
Innovation Solution
A high resolution clock signal generator using two programmable coarse delay circuits with phase-locked delay lines, where the first circuit delays pulses by Tp/N and the second by Tp/M, allowing a total delay resolution of Tp/(M*N) with N and M being relatively prime, enabling self-calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of logic gates in the delay line is increased to improve period resolution, then the delay resolution improves, but the device complexity and switching speed constraints worsen
Solution Approach 1:
The delay line is divided into multiple segments with different delay resolutions. The first delay circuit provides coarse delay with resolution Tp/N, while the second delay circuit provides fine delay with resolution Tp/M. This segmentation allows achieving high overall resolution Tp/(M*N) without requiring a single extremely complex delay line with M*N gates.
Solution Approach 2:
The patent transitions from a one-dimensional approach (single delay line with N gates) to a two-dimensional approach (series combination of two delay lines with N and M gates respectively). This dimensional change in the delay structure enables resolution multiplication while managing complexity through modular design.
2Measurement precision
If fine delay circuits are added to improve period resolution, then the delay resolution improves, but calibration time and complexity increase
Solution Approach 1:
The phase-locked delay lines automatically self-calibrate by locking onto the reference clock signal ROSC. The phase-lock mechanism ensures that the delay elements automatically adjust to provide precise delay values without requiring external calibration procedures, thereby eliminating time-consuming manual calibration while maintaining high resolution.
3Device complexity
If the number of logic gates is limited, then device complexity is reduced, but period resolution deteriorates
Solution Approach 1:
The patent combines two separate delay circuits with relatively prime gate counts N and M in series. The mathematical property of relatively prime numbers ensures that the combined delay resolution Tp/(M*N) is achieved with minimal total gates while maximizing the fine delay capability. This merging strategy leverages number theory to optimize the resolution-to-complexity ratio.
4Device complexity
If coarse delay circuits are used to reduce complexity, then device complexity is reduced, but delay resolution deteriorates
Solution Approach 1:
The overall delay function is segmented into two distinct circuits: a first coarse delay circuit providing Tp/N resolution and a second fine delay circuit providing Tp/M resolution. This segmentation allows each circuit to be optimized independently, with the first circuit handling large delay ranges and the second circuit providing fine adjustment, thereby achieving high overall resolution without excessive complexity in either individual circuit.
Data Source
AI summary
A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period Tp to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of Tp/N seconds over a range spanning Tp seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning Tp seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of Tp/(M*N) seconds when the integers N and M are relatively prime.