Clock Generator Using Dual Feedback Loops for Low-Jitter Output
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Solution Overview
Problem
Existing frequency locked loops (FLLs) in clock generators for integrated circuits face challenges in generating high-quality clock signals with low jitter, especially when the input clock is of poor quality or experiences frequency changes, leading to potential noise, distortion, and clock slippage in digital audio signal processing.
Innovation Solution
A clock generator design that utilizes two input clock signals, one with higher frequency accuracy and lower jitter, and another with higher jitter but appropriate frequency, to produce an output clock signal with desired frequency accuracy and low jitter through a frequency locked loop mechanism involving counters, digital filters, and a numerically controlled oscillator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single input clock signal is used in the FLL, then the device complexity is reduced, but the output clock jitter increases when the input clock quality is poor
Solution Approach 1:
The patent divides the clock input into two separate channels: a first input clock signal for frequency control and a second input clock signal for jitter filtering. This segmentation allows each clock signal to serve a specific function, enabling the system to achieve low jitter output even when individual input clocks have poor quality. The frequency comparator processes both clocks separately to generate distinct error signals that are then combined through digital filtering.
2Use of energy by moving object
If the input clock frequency changes (e.g., intermittent or burst mode), then power consumption is reduced, but clock slippage and data loss occur
Solution Approach 1:
The patent implements dual feedback loops where the first feedback loop uses the first input clock to control output frequency, and the second feedback loop uses the second input clock to maintain phase synchronization. When the first clock becomes intermittent, the second loop ensures continuous synchronization by providing a stable reference, preventing clock slippage and maintaining data integrity during power-saving modes.
3Ease of manufacture
If a predominantly digital solution is used with minimal external components, then ease of manufacture is improved, but achieving low jitter requires more complex circuitry
Solution Approach 1:
The patent replaces traditional analog jitter filtering mechanisms (which would require external capacitors and analog circuitry) with a fully digital filtering approach using digital signal processing. The digital filter processes the error signal from the frequency comparator to generate a filtered error signal that drives the numerically controlled oscillator, achieving low jitter output without requiring any external passive components and maintaining compatibility with standard CMOS fabrication processes.
Data Source
AI summary
A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.