Clock Generator Circuit With Phase-Divided Duty Control
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Solution Overview
Problem
In semiconductor memory devices, generating an internal clock with the same period and duty cycle as an external clock is challenging, especially when the external clock period is short, due to transistor characteristics, which affects synchronization and data output stability.
Innovation Solution
A clock generating circuit and method that divides the internal clock by N to produce 2N divided clocks with 360/2N-degree phase differences, using inverter groups and NAND combinations to generate clocks with constant duty and synchronized phases, ensuring the internal clock has the same period and 50:50 duty ratio as the external clock.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the external clock period is divided to generate an internal clock, then the internal operation can be synchronized, but the duty cycle adjustment becomes difficult due to transistor characteristics
Solution Approach 1:
The patent divides the internal clock by N to generate 2N divided clocks with phase differences of 360/2N degrees. By segmenting the clock generation into multiple phase-divided signals, the system achieves precise duty cycle control through logical combinations rather than relying on transistor characteristics alone. This segmentation enables independent control of clock phase and duty cycle.
Solution Approach 2:
The patent dynamically selects and combines divided clock signals using logical operations (NAND combinations) to generate the final clock signal. This dynamic combination approach allows the duty cycle to be adjusted by selecting appropriate phase-divided clocks, overcoming the static limitations of transistor-based duty cycle adjustment.
2Device complexity
If transistor characteristics are used for clock generation, then the circuit is simple, but the duty cycle cannot be precisely controlled
Solution Approach 1:
The patent introduces divided clocks as intermediary signals between the internal clock and the final output clock. These 2N phase-divided clocks serve as mediators that enable precise duty cycle control through logical combinations, bridging the gap between simple transistor-based generation and precise duty cycle requirements.
Solution Approach 2:
The patent changes the parameter of clock phase by generating 2N divided clocks with phase differences of 360/2N degrees. This parameter transformation allows the duty cycle to be controlled by selecting and combining specific phase-divided clocks, achieving precision without increasing transistor complexity.
3Device complexity
If the internal clock is generated without phase division, then the circuit is simpler, but synchronization with external clock becomes unstable
Solution Approach 1:
The patent segments the internal clock into 2N phase-divided clocks, each with a phase difference of 360/2N degrees. This segmentation provides multiple synchronized reference points that improve overall synchronization stability while maintaining a relatively simple circuit structure through systematic phase division.
Data Source
AI summary
A clock generating circuit generates a high frequency clock having a constant duty and the same period as that of an external clock. A clock generating circuit generates a clock signal (hereinafter “the clock”) used for outputting a data signal to a data pin. The clock generating circuit includes at least a dividing portion and a clock generating portion. A dividing portion divides an internal clock signal (hereinafter “the internal clock”) generated based on an external clock signal (hereinafter “the external clock”) and outputs a plurality of divided clock signals (hereinafter “the divided clocks”). The clock generating portion performs a predetermined logical operations combining the divided clocks to generate the clock having a constant duty and the same period as the external clock.