Closed-Loop Clock Generator for Duty Cycle Error Correction
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Solution Overview
Problem
Conventional clock generators for synchronous integrated circuits face issues with clock jitter, excessive power consumption, and slow operation due to the series arrangement of delay locked loops (DLLs) and duty cycle correction (DCC) circuits, which exacerbate timing errors and duty cycle errors at higher frequencies.
Innovation Solution
Implementing a clock generation circuit with DLL and DCC operations in parallel and utilizing closed-loop duty cycle correction to synchronize and correct the duty cycle of clock signals, reducing clock jitter and improving locking speed by adjusting delays in a closed-loop feedback mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If DLL and DCC circuits are arranged in series, then duty cycle correction is achieved, but clock jitter increases and locking speed decreases
Solution Approach 1:
The patent divides the clock generation system into two parallel independent paths: one path (DLL) handles phase synchronization and locking, while the other path (DCC) handles duty cycle correction. This segmentation allows each circuit to operate independently without compounding delays, reducing clock jitter while maintaining duty cycle correction capability.
2Manufacturing precision
If DLL and DCC circuits are arranged in series, then duty cycle correction is achieved, but locking speed becomes slow
Solution Approach 1:
The patent segments the clock generation function into parallel independent DLL and DCC circuits, allowing simultaneous operation. The DLL path locks phase quickly while the DCC path corrects duty cycle independently, eliminating the sequential dependency that caused slow locking speed in series arrangements.
3Speed
If clock frequency increases, then operating speed improves, but duty cycle error increases
Solution Approach 1:
The DCC circuit implements a feedback mechanism that continuously monitors the duty cycle of the output clock signal and dynamically adjusts the delay elements to maintain the desired 50% duty cycle. This feedback control allows the system to operate at high frequencies while automatically correcting duty cycle errors that arise from process variations and timing skew.
4Manufacturing precision
If series arrangement of DLL and DCC is used, then duty cycle correction is achieved, but power consumption increases
Solution Approach 1:
The patent segments the correction function into parallel independent DLL and DCC circuits with separate control logic. This allows each circuit to be optimized for its specific function and operated independently, reducing the overall power consumption compared to a series arrangement where all circuits must operate at full power to achieve the same correction效果.
Data Source
AI summary
Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal. By detecting the duty cycle error in the output signal, the clock generator may achieve improved performance that can correct accumulated duty cycle error and correct for duty cycle error introduced by the duty cycle corrector itself in some embodiments.