Clock Generator Using Duty Cycle Correction for PLL-Free Frequency Doubling
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Solution Overview
Problem
Conventional clock generators using phase-locked loops (PLL) or delay-locked loops (DLL) are complex, consume high power, and occupy large circuit areas, necessitating a novel approach for generating multiple frequency clock signals without these circuits.
Innovation Solution
A clock generator comprising a pulse generator and a duty cycle correction circuit, which adjusts the duty cycle of a pulse signal to produce an output clock signal with twice the frequency of the input, potentially using multiple frequency doublers in series to achieve higher multiples, thereby omitting the need for PLL or DLL circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If PLL or DLL circuits are used to generate multiple frequency clock signals, then frequency multiplication capability is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex PLL/DLL circuit blocks (phase detector, charge pump, loop filter, VCO, frequency divider) from the clock generation system. Instead, it uses a simplified architecture with only a pulse generator and duty cycle correction circuit, achieving frequency multiplication without the traditional complex feedback loops and control mechanisms.
Solution Approach 2:
The patent uses a pulse generator to create multiple pulse signals based on the input clock signal transitions, effectively copying the timing information multiple times within one clock period. This allows frequency multiplication by replicating pulse patterns rather than using complex frequency synthesis methods.
2Adaptability or versatility
If PLL or DLL circuits are used to generate multiple frequency clock signals, then frequency multiplication capability is achieved, but power consumption increases
Solution Approach 1:
The patent removes the power-hungry components of PLL/DLL circuits (charge pump, loop filter, voltage-controlled oscillator) and replaces them with a low-power pulse generator and duty cycle correction circuit. This extraction of essential functionality while eliminating power-intensive elements achieves frequency multiplication with significantly reduced power consumption.
3Adaptability or versatility
If PLL or DLL circuits are used to generate multiple frequency clock signals, then frequency multiplication capability is achieved, but circuit area increases
Solution Approach 1:
The patent extracts and eliminates multiple large circuit blocks (phase detector, charge pump, loop filter, VCO, frequency divider for PLL; or phase detector, charge pump, loop filter, voltage-controlled delay line for DLL) and replaces them with a compact pulse generator and duty cycle correction circuit. This dramatically reduces the occupied circuit area while maintaining frequency multiplication functionality.
4Manufacturing precision
If duty cycle correction circuit is added to achieve 50% duty cycle, then output quality is improved, but device complexity increases
Solution Approach 1:
The patent applies duty cycle correction only when necessary to achieve the desired 50% duty cycle output, rather than continuously adjusting. The correction circuit activates selectively based on the pulse generator output, providing precision only where needed while keeping the overall system simple.
Data Source
AI summary
A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.