Non-Overlapping Clock Generator With Adjustable Duty Cycles
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Solution Overview
Problem
Integrated receivers face challenges in achieving high sensitivity across multiple cellular bands due to the need for narrow band receive chains, which require multiple front ends and are affected by the duty cycle and non-overlapping characteristics of local oscillator signals, particularly in terms of phase noise and out-of-band rejection.
Innovation Solution
A non-overlapping clock generator is designed with plural pulse-generating modules connected in series, featuring adjustable duty cycles and low phase noise, where the enabling module triggers pulse-generating modules to ensure non-overlapping high voltage segments in the output signals, enabling efficient operation in receivers and other electronic systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If narrow band filters are used to achieve high sensitivity, then sensitivity is improved, but device complexity increases due to multiple front ends being required
Solution Approach 1:
The pulse-generating modules are divided into multiple independent units connected in series, where each module generates a specific non-overlapping clock signal. This segmentation allows the system to achieve multiple cellular band coverage through a single front end by using different duty cycle clock signals to tune the translational filter, thereby improving sensitivity without increasing device complexity through multiple front ends.
2Adaptability or versatility
If multiple front ends are used to cover multiple cellular bands, then band coverage is improved, but device complexity increases
Solution Approach 1:
The non-overlapping clock generator is designed as a universal circuit that can generate multiple different duty cycle clock signals (e.g., 20%, 40%, 60%, 80%) to tune a single translational filter for multiple cellular bands. This multi-functionality allows one front end to replace multiple front ends, achieving broad band coverage while reducing device complexity.
3Device complexity
If duty cycle of LO signals is not optimized, then device simplicity is maintained, but performance of translational filter deteriorates
Solution Approach 1:
The clock generator dynamically adjusts the duty cycle of LO signals by selectively enabling different pulse-generating modules. Each module is designed to produce a specific duty cycle (20%, 40%, 60%, 80%), and the enabling module selects the appropriate module based on the required cellular band. This dynamic adjustment optimizes translational filter performance across multiple bands while maintaining device simplicity through a single front end architecture.
Data Source
AI summary
A non-overlapping clock generator including an enabling module and N pulse-generating modules connected as a ring is provided. When the ith input node has a high voltage level, the enabling module enables the ith pulse-generating module so as to trigger the ith pulse-generating module to discharge the ith input node. After the ith input node has been discharged to a low voltage level, the ith pulse-generating module charges the ith output node to the high voltage level.