Clock Generator Circuit With Phase-Shifted Edge Timing Control
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Solution Overview
Problem
Existing clock generators and level shifters require high frequency performance to transmit clocks with high resolution, leading to increased costs due to the need for reduced wiring between components.
Innovation Solution
A clock generator system with a first and second clock generation circuit and a clock adjustment circuit that allows for fine adjustment of clock timing through phase-shifted pre-clocks and timing control signals, enabling precise control of rising and falling edges within a clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high frequency performance is used to transmit clock with high resolution, then clock transmission quality is improved, but cost increases
Solution Approach 1:
The clock transmission system is segmented into multiple serial interfaces: a first serial interface transmits the clock signal at a first frequency, while a second serial interface transmits data signals at a second frequency. This segmentation allows each interface to operate at optimized frequencies, reducing the need for high-frequency performance across all signal paths, thereby lowering cost while maintaining clock resolution.
Solution Approach 2:
The patent changes the frequency parameter of the clock signal by transmitting it at a reduced first frequency through the first serial interface, rather than maintaining the original high frequency. This parameter change enables standard-frequency wiring to be used, reducing manufacturing cost while the clock generation circuit compensates to maintain the required output clock resolution.
2Device complexity
If the number of wirings is reduced to transmit clock, then device complexity is reduced, but high-frequency performance is required which increases cost
Solution Approach 1:
The signal transmission is segmented into separate serial interfaces: the first serial interface is dedicated to clock signal transmission at a reduced frequency, while the second serial interface handles data signals. This segmentation reduces the need for high-frequency wiring performance, allowing simpler, lower-cost wiring implementations while maintaining signal integrity.
Solution Approach 2:
The patent uses serial transmission to copy the clock signal through the first serial interface at a reduced frequency, rather than transmitting the original high-frequency clock directly. This copying at lower frequency enables the use of simpler wiring with fewer performance requirements, reducing device complexity and manufacturing cost.
3Device complexity
If high-performance clock generator is used to reduce wiring, then wiring complexity is reduced, but cost increases
Solution Approach 1:
The clock generation functionality is segmented from the main display driver circuit into a separate first clock generation circuit. This circuit generates the clock signal at a reduced first frequency, which is then transmitted through the first serial interface. This segmentation allows the use of standard-frequency components and wiring, reducing overall system cost while maintaining the required clock performance at the output.
Solution Approach 2:
The first clock generation circuit changes the frequency parameter of the generated clock signal, outputting it at a reduced first frequency rather than the original high frequency. This parameter change enables the use of lower-performance, lower-cost wiring and components throughout the system, reducing manufacturing cost while the timing controller compensates to maintain the required output clock characteristics.
Data Source
AI summary
The present disclosure relates to a clock generator and a display device including the same. The clock generator includes a first clock generation circuit configured to output a clock, data, and a timing control signal; a first wiring through which the clock is serially transmitted; a second wiring through which the data is serially transmitted; a third wiring through which a pulse of the timing control signal is serially transmitted; a second clock generation circuit connected to the first clock generation circuit through the first wiring, the second wiring, and the third wiring and configured to generate pre-clocks in which phases are sequentially shifted based on the data and the clock; and a clock adjustment circuit configured to receive the pulse of the timing control signal and the pre-clock and output an output clock.