Clock Generator Fast Lock During Power Supply Voltage Ramping
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Solution Overview
Problem
Clock generating circuits in mobile devices experience long settling times during dynamic power supply voltage ramping, leading to significant phase errors and inefficient frequency stabilization.
Innovation Solution
The implementation of a clock generating circuit with open feedback loop switch logic and a dynamic fast lock control signal generator, which selectively opens and closes the feedback loop during power supply voltage ramping, applying a stabilizing control signal to the variable clock signal generator to quickly lock onto the desired frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the feedback loop is closed during power supply voltage ramping to maintain frequency control, then frequency stability is maintained, but settling time increases significantly and phase errors accumulate
Solution Approach 1:
The system performs preliminary actions by detecting the power supply voltage ramping condition before it occurs and proactively opening the feedback loop switch in advance. This prevents the phase accumulator from accumulating large phase errors during the ramping period, thereby reducing the settling time required after ramping completes while maintaining frequency stability through subsequent fast lock mechanisms.
2Loss of time
If the feedback loop is opened during power supply voltage ramping to reduce phase errors, then settling time is reduced, but frequency control is lost during the transition
Solution Approach 1:
The system uses feedback by continuously monitoring the power supply voltage ramping condition through detection circuits. When ramping is detected, the feedback loop switch is opened to prevent phase errors. After ramping completes, the system uses fast lock mechanisms with updated reference frequencies to rapidly re-establish frequency control, ensuring both reduced settling time and maintained frequency stability.
Solution Approach 2:
The feedback loop switch transitions from a static closed state to a dynamic state that adapts to power supply conditions. The switch opens during detected ramping periods and closes when ramping completes, allowing the system to optimize performance based on real-time operating conditions. This dynamic behavior enables both reduced phase errors during transitions and maintained frequency control during normal operation.
3Measurement precision
If traditional PLL control is used during power supply voltage changes, then frequency accuracy is maintained, but mode transition speed decreases
Solution Approach 1:
The system skips the traditional slow PLL settling process by opening the feedback loop during power supply ramping to prevent phase error accumulation. After ramping completes, fast lock mechanisms rapidly adjust the VCO frequency to the target value, bypassing the conventional gradual phase-adjustment process. This enables mode transitions to complete in minimal time while maintaining frequency accuracy through the fast lock mechanism.
Data Source
AI summary
In a method and apparatus for using a clock generating circuit to minimize settling time after dynamic power supply voltage ramping, a clock signal may be generated using a clock generating circuit having, among other things, open feedback loop switch logic and a dynamic fast lock control signal generator. Whereupon, when in operation, the open feedback loop switch logic is responsive to a controlled change in power supply voltage condition such that a feedback loop of the clock generating circuit is opened during power supply voltage ramping (e.g., during transitions to or from battery conservation modes). In response to opening the feedback loop, the dynamic fast lock control signal generator selectively applies a stabilizing control signal to a variable clock signal generator (e.g., a voltage controlled oscillator) such that the generated clock signal can quickly lock onto the proper target frequency.