Reference-Locked Clock Generator With Gated Ring-Oscillator Injection
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Solution Overview
Problem
Phase Locked Loops (PLLs) face bandwidth limitations, leading to slow frequency settling times, particularly in high-frequency clocking conditions required for precision in digital logic circuits like microprocessors.
Innovation Solution
A method and apparatus that utilize a reference clock gating circuit to enable a ring-oscillator-injection mode and a ring-oscillator-closed-loop mode, allowing for adjustable propagation delays in a buffer chain to improve frequency settling times by selectively injecting a reference clock signal and enabling continuous oscillation independent of reference clock transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a closed-loop PLL architecture is used to synchronize the digital clock, then the phase locking function is achieved, but the bandwidth limitations cause slow frequency settling times
Solution Approach 1:
The patent applies preliminary action by injecting the reference clock signal into the ring oscillator buffer chain before the PLL locking process completes. This pre-synchronization of the buffer chain phase with the reference clock allows the oscillator to settle faster once locked, reducing the overall frequency settling time while maintaining reliable phase locking.
Solution Approach 2:
The patent implements dynamics by switching between two operational modes: a closed-loop mode during normal operation and an injection mode during startup or transient conditions. This dynamic mode switching allows the system to optimize performance for different operational states, achieving fast settling during transients while maintaining stable phase locking during normal operation.
2Loss of time
If the reference clock signal is continuously injected into the ring oscillator, then the frequency settling time is reduced, but the oscillation may become independent of the feedback loop
Solution Approach 1:
The patent applies periodic action by injecting the reference clock signal only during specific intervals (startup or transient conditions) rather than continuously. The injection is timed to occur when needed for fast settling, and then stopped to allow the feedback loop to maintain control, thus preserving both fast settling and reliable feedback loop operation.
Solution Approach 2:
The patent maintains continuity of useful action by ensuring that the buffer chain remains synchronized with the reference clock through periodic injection events, while the feedback loop continuously maintains phase locking. This continuous coordination between injection events and feedback control ensures uninterrupted reliable operation.
Data Source
AI summary
Clock generation from an external reference by generating a reference clock gating signal using a reference clock gating circuit; enabling a ring-oscillator-injection mode using the reference clock gating signal to disable a first buffer of a ring oscillator and to enable a reference clock injection buffer, the first buffer and the injection buffer having parallel connected outputs that connect to a next buffer input; receiving a reference clock transition of a reference clock signal at the injection buffer and injecting it into the next buffer; and enabling a ring-oscillator-closed-loop mode by using the reference clock gating signal to enable the first buffer and to disable the reference clock injection buffer.