Clock Generator Jitter Correction for Stable High-Frequency Signals

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Solution Overview

Problem

Conventional clock signal generation systems are inadequate for producing stable high-frequency clock signals, as they often rely on expensive and impractical high-precision crystals and oscillators, leading to accuracy and agility issues, especially when multiplying low-frequency reference clock signals to achieve high-frequency outputs.

Innovation Solution

A clock generator system that includes a source clock generating a low-frequency reference signal, a clock multiplier to increase the frequency by a predetermined factor, and a jitter measurement module that uses both the high-frequency clock signal and a jitter reference signal to generate a compensation signal, which is then adjusted to correct for jitter, thereby ensuring a stable and accurate high-frequency output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high-precision crystals and oscillators are used to generate high-frequency clock signals, then frequency stability is improved, but cost and device complexity increase significantly

Engineering Contradiction:
Improvefrequency stabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The clock generation system is divided into multiple functional modules: a low-frequency reference oscillator, a clock multiplier stage, and a jitter correction module. This segmentation allows each module to operate at optimized frequencies, with the reference oscillator running at a lower, more stable frequency while the clock multiplier handles frequency conversion, thereby reducing the need for expensive high-precision components across the entire system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A jitter correction module acts as an intermediary between the clock multiplier output and the final clock signal. This module measures and corrects jitter introduced during frequency multiplication, enabling the use of lower-cost reference oscillators while maintaining high-frequency output stability through active correction rather than relying solely on expensive high-precision crystals.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If low-frequency reference oscillators are used to generate high-frequency clock signals through multiplication, then cost is reduced, but jitter increases

Engineering Contradiction:
ImprovecostVSAvoidjitter
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The jitter correction module implements a feedback mechanism that continuously monitors the jitter in the multiplied clock signal and applies corrective adjustments. This feedback loop measures the actual jitter performance and dynamically compensates for it, allowing the system to use cost-effective low-frequency reference oscillators while maintaining low jitter in the final high-frequency output.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system changes the operating parameters of the reference oscillator, running it at a lower frequency where high-precision crystals are more practical and less costly. The jitter correction module then adjusts temporal parameters of the multiplied signal to compensate for jitter, effectively separating the cost-saving frequency reduction from the jitter problem through parameter transformation and correction.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If clock multiplication is used to achieve high-frequency outputs, then frequency agility is improved, but phase noise and jitter are amplified

Engineering Contradiction:
Improvefrequency agilityVSAvoidphase noise
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The jitter correction module serves as an intermediary that cleans up the phase noise and jitter introduced by the clock multiplier. It measures the degraded signal quality after multiplication and applies corrective timing adjustments, enabling the system to benefit from the frequency agility of clock multiplication while mitigating its harmful effects on phase noise and jitter.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system accepts the jitter and phase noise amplification as an inevitable byproduct of clock multiplication but converts this harmful effect into a measurable parameter that can be corrected. By measuring the jitter introduced by multiplication and applying compensating adjustments, the system transforms the problem of amplified noise into an opportunity for precise correction and optimization.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11231741B1Systems and methods for generating clock signals
Publication Date: 2022.01.25 MARVELL ASIA PTE LTD
  • US11231741B1 patent drawing
  • US11231741B1 patent drawing
  • US11231741B1 patent drawing

AI summary

The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a clock generator that includes a source clock generates a source clock signal at a low frequency. A clock multiplier multiplies the source clock signal by a predetermined factor to generate a high frequency clock signal. The high frequency clock signal is corrected by a time adjustment module by applying a compensation signal. The compensation signal is determined by a jitter measurement module, which uses both the high frequency clock signal and a jitter reference signal to determine the compensation signal. There are other embodiments as well.